Semiconductor & Computer Engineering
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| Date | Name | Thumbnail | Size | User | Description | Versions |
|---|---|---|---|---|---|---|
| 13:39, 1 July 2017 | vy86c610.pdf (file) |  |
5.43 MB | At32Hz | VLSI Technology {{vti|VY86C610}} | 1 |
| 14:48, 1 July 2017 | vlsi arm710-610.pdf (file) |  |
493 KB | At32Hz | VLSI Technology {{vti|VY86C710}} / {{vti|VY86C610C}} | 1 |
| 18:25, 1 July 2017 | vlsi arm810-710.pdf (file) | Error creating thumbnail: convert: no decode delegate for this image format `' @ error/constitute.c/ReadImage/501. convert: no images defined `/tmp/transform_b555303a3141.jpg' @ error/convert.c/ConvertImageCommand/3241. |
507 KB | At32Hz | VLSI {{vti|VY86C810}} & {{vti|VY86C710A2}} | 1 |
| 17:08, 2 July 2017 | core i9x logo.png (file) |  |
540 KB | Inject | Intel {{intel|Core i9}}X logo, Introduced May 30, 2017 | 1 |
| 00:40, 4 July 2017 | kaby lake u (front; iris).png (file) | .png) |
714 KB | David | Front of {{intel|Kaby Lake U|l=core}} package by Intel Press. Copyright of Intel. This chip is a Kaby Lake U with Iris Plus GPU and an OPC. | 1 |
| 00:53, 4 July 2017 | skylake u (front; iris).png (file) | .png) |
714 KB | ChipIt | Front of {{intel|Kaby Lake U|l=core}} package by Intel Press. Copyright of Intel. This chip is a Kaby Lake U with Iris Plus GPU and an OPC. | 1 |
| 21:58, 4 July 2017 | benchmarks.svg (file) |  |
3 KB | ChipIt | Own Benchmark drawing. | 1 |
| 13:12, 7 July 2017 | skylake u (back; standard).png (file) | .png) |
9.82 MB | ChipIt | Back of {{intel|Skylake U|l=core}} package by Intel Press. Copyright of Intel. This chip is a Skylake U non-Iris (without OPC) | 1 |
| 13:12, 7 July 2017 | skylake u (back; iris).png (file) | .png) |
31.11 MB | ChipIt | Back of {{intel|Skylake U|l=core}} package by Intel Press. Copyright of Intel. This chip is a Skylake U with Iris Plus GPU and an OPC. | 1 |
| 13:14, 7 July 2017 | skylake u (front; iris) angled.png (file) | _angled.png) |
20.12 MB | ChipIt | Front of {{intel|Skylake U|l=core}} package by Intel Press. Copyright of Intel. This chip is a Skylake U with Iris Plus GPU and an OPC. | 1 |
| 01:11, 10 July 2017 | Intel Advanced Vector Extensions 2015-2016 Support in GNU Compiler Collection.pdf (file) |  |
1.46 MB | David | * Intel® {{x86|AVX-512|Advanced Vector Extensions}} 2015/2016 * Support in GNU Compiler Collection * GNU Tools Cauldron 2014 * Presented by Kirill Yukhin of Intel, July 2014 | 1 |
| 05:48, 10 July 2017 | arm3 cache.svg (file) |  |
42 KB | At32Hz | =={{int:filedesc}}== {{Information |description=My own drawing of Acorn's {{acorn|ARM3|l=arch}} cache |date=2017 |source=Own Work. |author=At32Hz |permission={{wikichip-license}} |other_versions= |other_fields= }} | 1 |
| 17:27, 10 July 2017 | arm250 ds.pdf (file) |  |
8.04 MB | At32Hz | {{armh|ARM250|l=arch}} Data Sheet | 1 |
| 19:34, 10 July 2017 | arm250 block diagram.svg (file) |  |
39 KB | At32Hz | was incomplete | 2 |
| 22:17, 10 July 2017 | intel 4004 chip.jpg (file) |  |
39 KB | David | Intel {{intel|4004}}. Image by Intel. | 1 |
| 16:54, 11 July 2017 | skylake sp (basic).png (file) | .png) |
1.21 MB | David | 2 | |
| 15:40, 12 July 2017 | xeon bronze (2017).png (file) | .png) |
980 KB | ChipIt | New high resolution, transparent pngs from Intel | 3 |
| 15:41, 12 July 2017 | xeon silver (2017).png (file) | .png) |
968 KB | ChipIt | New high resolution, transparent pngs from Intel | 3 |
| 15:41, 12 July 2017 | xeon gold (2017).png (file) | .png) |
962 KB | ChipIt | New high resolution, transparent pngs from Intel | 3 |
| 15:41, 12 July 2017 | xeon platinum (2017).png (file) | .png) |
982 KB | ChipIt | New high resolution, transparent pngs from Intel | 3 |
| 04:39, 13 July 2017 | xeon scalable family decode.png (file) |  |
392 KB | David | {{intel|Skylake SP|l=core}} family decode from previous brands. | 1 |
| 07:02, 13 July 2017 | skylake server cache bandwidth.svg (file) |  |
10 KB | At32Hz | Intel {{intel|Skylake|l=arch}} server configuration cache bandwidth | 1 |
| 07:18, 13 July 2017 | skylake scheduler server.svg (file) |  |
55 KB | At32Hz | Intel {{intel|Skylake|l=arch}} server scheduler | 1 |
| 07:28, 13 July 2017 | intel xeon skylake sp.jpg (file) |  |
2.26 MB | At32Hz | Intel {{intel|Skylake SP|l=core}} based processors. Image by Intel. | 1 |
| 19:58, 13 July 2017 | mixed avx-normal workloads with avx512.png (file) |  |
191 KB | At32Hz | Intel's {{intel|Frequency Behavior}} from a slide by Intel | 1 |
| 21:48, 13 July 2017 | avx-512 flops.png (file) |  |
654 KB | David | Intel {{x86|AVX-512}} FLOPS | 1 |
| 03:00, 14 July 2017 | skylake sp xcc die config.png (file) |  |
385 KB | At32Hz | Die configuration of the {{intel|Skylake|l=arch}} SP XCC die. Image by Intel. | 1 |
| 06:40, 14 July 2017 | skylake-sp (hfi).png (file) | .png) |
1.41 MB | At32Hz | Front view of the Intel {{intel|Skylake SP|l=core}} core based chip with integrated Host Fabric Interface (HFI). Image by Intel. | 1 |
| 00:25, 15 July 2017 | skylake sp 2-way 2 upi.svg (file) |  |
436 KB | At32Hz | corrected mems more accurately | 2 |
| 00:25, 15 July 2017 | skylake sp 2-way 3 upi.svg (file) |  |
436 KB | At32Hz | corrected mems more accurately | 2 |
| 00:25, 15 July 2017 | skylake sp 4-way 2 upi.svg (file) |  |
436 KB | At32Hz | corrected mems more accurately | 2 |
| 00:25, 15 July 2017 | skylake sp 8-way 3 upi.svg (file) |  |
436 KB | At32Hz | corrected mems more accurately | 3 |
| 01:35, 15 July 2017 | omni-path ift carrier.png (file) |  |
807 KB | At32Hz | Intel {{intel|Omni-Path}} IFT carrier. As used in the {{intel|Knights Landing|l=arch}} and {{intel|Skylake|l=arch}} server configuration. Image by Intel. | 1 |
| 01:46, 15 July 2017 | skylake sp with hfi to carrier.png (file) |  |
1.49 MB | At32Hz | Intel {{intel|Skylake|l=arch}} SP with HFI to carrier. | 1 |
| 10:43, 15 July 2017 | skylake sp buffer windows.png (file) |  |
884 KB | David | Intel {{intel|Skylake|l=arch}} {{intel|SP|l=core}} Buffer Windows by Intel | 1 |
| 14:14, 15 July 2017 | skylake sp added cach and vpu.png (file) |  |
78 KB | David | Intel {{intel|Skylake|l=arch}} SP, core extended with cache and VPU | 1 |
| 18:28, 15 July 2017 | snc clusters.png (file) |  |
409 KB | David | Intel {{intel|Skylake|l=arch}} server SNC sub-NUMA clusters. Image by Intel, WikiChip added annotation. | 1 |
| 02:25, 16 July 2017 | intel-xeon-scalable-processors-product-brief.pdf (file) |  |
1.19 MB | ChipIt | Intel Xeon ({{intel|Skylake SP|l=core}}) Processors Product Brief. | 1 |
| 02:25, 16 July 2017 | intel-xeon-scalable-processors-overview.pdf (file) |  |
2.84 MB | ChipIt | Intel Xeon ({{intel|Skylake SP|l=core}}) Processors Product Overview. | 1 |
| 13:17, 16 July 2017 | skylake sp 4-way 3 upi.svg (file) |  |
437 KB | At32Hz | 3 | |
| 20:03, 16 July 2017 | broadwell avx turbo changes.png (file) |  |
538 KB | At32Hz | Intel {{intel|Broadwell|l=arch}} {{x86|AVX2}} turbo changes. From Intel's presentation. | 1 |
| 14:23, 20 July 2017 | 2015 InvestorMeeting Bill Holt WEB2.pdf (file) |  |
3.99 MB | At32Hz | * Advancing Moore's law * Bill Holt * Executive Vice President | 1 |
| 15:52, 20 July 2017 | ibm 14nm m1 cx.png (file) |  |
128 KB | At32Hz | IBM 14 nm process M1 cross-section. Image by IBM | 1 |
| 15:53, 20 July 2017 | ibm 14nm m2 cx.png (file) |  |
144 KB | At32Hz | IBM 14 nm process M2 cross-section. Image by IBM. | 1 |
| 18:12, 20 July 2017 | z14 core layout.png (file) |  |
551 KB | Inject | IBM {{ibm|z14|l=arch}} core layout. Image by IBM. | 1 |
| 20:24, 20 July 2017 | renesas r-car logo.png (file) |  |
77 KB | BCD | Renesas {{renesas|R-Car}} logo | 1 |
| 21:10, 20 July 2017 | r-car h1.png (file) |  |
1.67 MB | BCD | Renesas R-Car H1, Image by Renesas | 1 |
| 23:05, 20 July 2017 | rcar h1.gif (file) |  |
64 KB | BCD | Renesas R-Car H1, block diagram by Renesas. | 1 |
| 03:19, 21 July 2017 | amd gpu roadmap.png (file) |  |
443 KB | Nible | AMD gpu roadmap | 1 |
| 11:58, 21 July 2017 | rcar m1s.gif (file) |  |
56 KB | BCD | Renesas R-Car M1S, by Renesas | 1 |
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