Semiconductor & Computer Engineering
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Information for "via technologies/microarchitectures/esther"
Basic information
| Display title | Esther - Microarchitectures - VIA Technologies |
| Default sort key | Esther, VIA Technologies |
| Page length (in bytes) | 462 |
| Page ID | 27778 |
| Page content language | English (en) |
| Page content model | wikitext |
| Indexing by robots | Allowed |
| Number of redirects to this page | 0 |
| Counted as a content page | Yes |
| Number of subpages of this page | 0 (0 redirects; 0 non-redirects) |
Page protection
| Edit | Allow all users (infinite) |
| Move | Allow all users (infinite) |
Edit history
| Page creator | At32Hz (talk | contribs) |
| Date of page creation | 21:22, 14 January 2018 |
| Latest editor | At32Hz (talk | contribs) |
| Date of latest edit | 21:22, 14 January 2018 |
| Total number of edits | 1 |
| Total number of distinct authors | 1 |
| Recent number of edits (within past 90 days) | 0 |
| Recent number of distinct authors | 0 |
Page properties
| Transcluded templates (6) | Templates used on this page:
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Facts about "Esther - Microarchitectures - VIA Technologies"
| codename | Esther + |
| core count | 1 + |
| designer | VIA Technologies + |
| full page name | via technologies/microarchitectures/esther + |
| instance of | microarchitecture + |
| instruction set architecture | x86-32 + |
| manufacturer | TSMC + |
| microarchitecture type | CPU + |
| name | Esther + |
| pipeline stages | 16 + |
| process | 90 nm (0.09 μm, 9.0e-5 mm) + |