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Information for "umich/microarchitectures/vanilla-5"
Basic information
| Display title | Vanilla-5 - Microarchitectures |
| Default sort key | umich/microarchitectures/vanilla-5 |
| Page length (in bytes) | 2,980 |
| Page ID | 35752 |
| Page content language | English (en) |
| Page content model | wikitext |
| Indexing by robots | Allowed |
| Number of redirects to this page | 1 |
| Counted as a content page | Yes |
| Number of subpages of this page | 0 (0 redirects; 0 non-redirects) |
Page protection
| Edit | Allow all users (infinite) |
| Move | Allow all users (infinite) |
Edit history
| Page creator | David (talk | contribs) |
| Date of page creation | 22:38, 12 January 2020 |
| Latest editor | David (talk | contribs) |
| Date of latest edit | 17:35, 20 January 2020 |
| Total number of edits | 5 |
| Total number of distinct authors | 1 |
| Recent number of edits (within past 90 days) | 0 |
| Recent number of distinct authors | 0 |
Page properties
| Transcluded templates (9) | Templates used on this page:
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Facts about "Vanilla-5 - Microarchitectures"
| codename | Vanilla-5 + |
| designer | University of Michigan +, University of California + and Cornell University + |
| full page name | umich/microarchitectures/vanilla-5 + |
| instance of | microarchitecture + |
| instruction set architecture | RISC-V + |
| manufacturer | TSMC + |
| microarchitecture type | CPU + |
| name | Vanilla-5 + |
| pipeline stages | 5 + |
| process | 16 nm (0.016 μm, 1.6e-5 mm) + |