Semiconductor & Computer Engineering
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Information for "movidius/sabre"
Basic information
| Display title | SABRE - Intel Movidius |
| Default sort key | SABRE, Movidius |
| Page length (in bytes) | 1,448 |
| Page ID | 28591 |
| Page content language | English (en) |
| Page content model | wikitext |
| Indexing by robots | Allowed |
| Number of redirects to this page | 2 |
| Counted as a content page | Yes |
| Number of subpages of this page | 0 (0 redirects; 0 non-redirects) |
Page protection
| Edit | Allow all users (infinite) |
| Move | Allow all users (infinite) |
Edit history
| Page creator | David (talk | contribs) |
| Date of page creation | 22:19, 10 March 2018 |
| Latest editor | At32Hz (talk | contribs) |
| Date of latest edit | 10:31, 11 March 2018 |
| Total number of edits | 6 |
| Total number of distinct authors | 2 |
| Recent number of edits (within past 90 days) | 0 |
| Recent number of distinct authors | 0 |
Page properties
| Transcluded templates (10) | Templates used on this page:
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Facts about "SABRE - Intel Movidius"
| base frequency | 180 MHz (0.18 GHz, 180,000 kHz) + |
| core count | 9 + |
| designer | Movidius + |
| full page name | movidius/sabre + |
| instance of | microprocessor + |
| isa | SPARC V8 + and SHAVE + |
| isa family | SPARC + and SHAVE + |
| ldate | 1900 + |
| manufacturer | TSMC + |
| market segment | Embedded + and Mobile + |
| microarchitecture | LEON3 + and SHAVE v2.0 + |
| model number | SABRE + |
| name | SABRE + |
| process | 65 nm (0.065 μm, 6.5e-5 mm) + |
| technology | CMOS + |
| thread count | 9 + |
| word size | 32 bit (4 octets, 8 nibbles) + |