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Information for "intel/microarchitectures/silvermont"
Basic information
| Display title | Silvermont - Microarchitectures - Intel |
| Default sort key | Silvermont, Intel |
| Page length (in bytes) | 9,035 |
| Page ID | 6594 |
| Page content language | English (en) |
| Page content model | wikitext |
| Indexing by robots | Allowed |
| Number of redirects to this page | 3 |
| Counted as a content page | Yes |
| Number of subpages of this page | 0 (0 redirects; 0 non-redirects) |
Page protection
| Edit | Allow all users (infinite) |
| Move | Allow all users (infinite) |
Edit history
| Page creator | At32Hz (talk | contribs) |
| Date of page creation | 10:19, 9 April 2016 |
| Latest editor | 94.114.86.143 (talk) |
| Date of latest edit | 08:35, 25 September 2019 |
| Total number of edits | 36 |
| Total number of distinct authors | 8 |
| Recent number of edits (within past 90 days) | 0 |
| Recent number of distinct authors | 0 |
Page properties
| Transcluded templates (12) | Templates used on this page:
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Facts about "Silvermont - Microarchitectures - Intel"
| codename | Silvermont + |
| core count | 1 +, 2 +, 4 + and 8 + |
| designer | Intel + |
| first launched | 2013 + |
| full page name | intel/microarchitectures/silvermont + |
| instance of | microarchitecture + |
| instruction set architecture | x86-64 + |
| manufacturer | Intel + |
| microarchitecture type | CPU + |
| name | Silvermont + |
| phase-out | 2015 + |
| pipeline stages (max) | 14 + |
| pipeline stages (min) | 12 + |
| process | 22 nm (0.022 μm, 2.2e-5 mm) + |