-
WikiChip
WikiChip
-
Architectures
Popular x86
-
Intel
- Client
- Server
- Big Cores
- Small Cores
-
AMD
Popular ARM
-
ARM
- Server
- Big
- Little
-
Cavium
-
Samsung
-
-
Chips
Popular Families
-
Ampere
-
Apple
-
Cavium
-
HiSilicon
-
MediaTek
-
NXP
-
Qualcomm
-
Renesas
-
Samsung
-
From WikiChip
Information for "intel/microarchitectures/goldmont"
Basic information
Display title | intel/microarchitectures/goldmont |
Default sort key | intel/microarchitectures/goldmont |
Page length (in bytes) | 6,958 |
Page ID | 6614 |
Page content language | English (en) |
Page content model | wikitext |
Indexing by robots | Allowed |
Number of redirects to this page | 4 |
Number of subpages of this page | 0 (0 redirects; 0 non-redirects) |
Page protection
Edit | Allow all users (infinite) |
Move | Allow all users (infinite) |
Edit history
Page creator | At32Hz (talk | contribs) |
Date of page creation | 22:17, 9 April 2016 |
Latest editor | David (talk | contribs) |
Date of latest edit | 22:05, 23 March 2020 |
Total number of edits | 52 |
Total number of distinct authors | 12 |
Recent number of edits (within past 90 days) | 0 |
Recent number of distinct authors | 0 |
Retrieved from "https://en.wikichip.org/wiki/intel/microarchitectures/goldmont"
Facts about "Goldmont - Microarchitectures - Intel"
codename | Goldmont + |
core count | 2 +, 4 +, 8 +, 12 + and 16 + |
designer | Intel + |
first launched | August 30, 2016 + |
full page name | intel/microarchitectures/goldmont + |
instance of | microarchitecture + |
instruction set architecture | x86-64 + |
manufacturer | Intel + |
microarchitecture type | CPU + |
name | Goldmont + |
pipeline stages (max) | 14 + |
pipeline stages (min) | 12 + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |