From WikiChip
Information for "intel/microarchitectures/amber lake"
Basic information
Display title | Amber Lake - Microarchitectures - Intel |
Default sort key | Amber Lake, Intel |
Page length (in bytes) | 4,522 |
Page ID | 30250 |
Page content language | English (en) |
Page content model | wikitext |
Indexing by robots | Allowed |
Number of redirects to this page | 2 |
Counted as a content page | Yes |
Number of subpages of this page | 0 (0 redirects; 0 non-redirects) |
Page protection
Edit | Allow all users (infinite) |
Move | Allow all users (infinite) |
Edit history
Page creator | At32Hz (talk | contribs) |
Date of page creation | 22:56, 4 June 2018 |
Latest editor | David (talk | contribs) |
Date of latest edit | 08:03, 24 May 2019 |
Total number of edits | 11 |
Total number of distinct authors | 4 |
Recent number of edits (within past 90 days) | 0 |
Recent number of distinct authors | 0 |
Page properties
Transcluded templates (18) | Templates used on this page:
|
Facts about "Amber Lake - Microarchitectures - Intel"
codename | Amber Lake + |
core count | 2 + |
designer | Intel + |
first launched | April 2018 + |
full page name | intel/microarchitectures/amber lake + |
instance of | microarchitecture + |
instruction set architecture | x86-64 + |
manufacturer | Intel + |
microarchitecture type | CPU + |
name | Amber Lake + |
pipeline stages (max) | 19 + |
pipeline stages (min) | 14 + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |