From WikiChip
Information for "intel/cores/coffee lake r"
Basic information
| Display title | Coffee Lake R - Cores - Intel |
| Default sort key | Coffee Lake R, Intel |
| Page length (in bytes) | 3,728 |
| Page ID | 28024 |
| Page content language | English (en) |
| Page content model | wikitext |
| Indexing by robots | Allowed |
| Number of redirects to this page | 4 |
| Counted as a content page | Yes |
| Number of subpages of this page | 0 (0 redirects; 0 non-redirects) |
Page protection
| Edit | Allow all users (infinite) |
| Move | Allow all users (infinite) |
Edit history
| Page creator | At32Hz (talk | contribs) |
| Date of page creation | 12:55, 1 February 2018 |
| Latest editor | David (talk | contribs) |
| Date of latest edit | 00:38, 7 May 2019 |
| Total number of edits | 19 |
| Total number of distinct authors | 7 |
| Recent number of edits (within past 90 days) | 0 |
| Recent number of distinct authors | 0 |
Page properties
| Transcluded templates (19) | Templates used on this page:
|
Facts about "Coffee Lake R - Cores - Intel"
| Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Coffee Lake R - Cores - Intel#package + |
| designer | Intel + |
| first announced | October 8, 2018 + |
| first launched | October 19, 2018 + |
| instance of | core + |
| isa | x86-64 + |
| isa family | x86 + |
| manufacturer | Intel + |
| microarchitecture | Coffee Lake + |
| name | Coffee Lake R + |
| package | FCLGA-1151 + |
| process | 14 nm (0.014 μm, 1.4e-5 mm) + |
| socket | LGA-1151 + |
| technology | CMOS + |
| word size | 64 bit (8 octets, 16 nibbles) + |