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Information for "fujitsu/sparc64"
Basic information
Display title | SPARC64 - Fujitsu |
Default sort key | SPARC64, Fujitsu |
Page length (in bytes) | 3,873 |
Page ID | 17391 |
Page content language | English (en) |
Page content model | wikitext |
Indexing by robots | Allowed |
Number of redirects to this page | 0 |
Counted as a content page | Yes |
Number of subpages of this page | 1 (0 redirects; 1 non-redirect) |
Page protection
Edit | Allow all users (infinite) |
Move | Allow all users (infinite) |
Edit history
Page creator | David (talk | contribs) |
Date of page creation | 18:22, 12 April 2017 |
Latest editor | David (talk | contribs) |
Date of latest edit | 18:22, 12 April 2017 |
Total number of edits | 1 |
Total number of distinct authors | 1 |
Recent number of edits (within past 90 days) | 0 |
Recent number of distinct authors | 0 |
Page properties
Transcluded templates (15) | Templates used on this page:
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Facts about "SPARC64 - Fujitsu"
designer | Fujitsu + and HAL Computer Systems + |
first announced | November 1995 + |
first launched | November 1995 + |
full page name | fujitsu/sparc64 + |
instance of | microprocessor family + |
main designer | Fujitsu + |
manufacturer | Fujitsu + and TSMC + |
microarchitecture | SPARC64* + |
name | SPARC64 + |
process | 400 nm (0.4 μm, 4.0e-4 mm) +, 350 nm (0.35 μm, 3.5e-4 mm) +, 250 nm (0.25 μm, 2.5e-4 mm) +, 150 nm (0.15 μm, 1.5e-4 mm) +, 130 nm (0.13 μm, 1.3e-4 mm) +, 90 nm (0.09 μm, 9.0e-5 mm) +, 65 nm (0.065 μm, 6.5e-5 mm) +, 45 nm (0.045 μm, 4.5e-5 mm) +, 40 nm (0.04 μm, 4.0e-5 mm) +, 28 nm (0.028 μm, 2.8e-5 mm) + and 20 nm (0.02 μm, 2.0e-5 mm) + |
technology | CMOS + |
word size | 64 bit (8 octets, 16 nibbles) + |