Information for "cavium/thunderx2"

Basic information

Display title	ThunderX2 - Cavium
Default sort key	ThunderX2, Cavium
Page length (in bytes)	3,962
Page ID	30247
Page content language	English (en)
Page content model	wikitext
Indexing by robots	Allowed
Number of redirects to this page	7
Counted as a content page	Yes
Number of subpages of this page	6 (0 redirects; 6 non-redirects)

Edit	Allow all users (infinite)
Move	Allow all users (infinite)

Page creator	At32Hz (talk \| contribs)
Date of page creation	00:55, 4 June 2018
Latest editor	David (talk \| contribs)
Date of latest edit	19:33, 26 April 2019
Total number of edits	18
Total number of distinct authors	6
Recent number of edits (within past 90 days)	0
Recent number of distinct authors	0

Transcluded templates (23)	Templates used on this page: Template:!- (edit) Template:\\ (edit) Template:arch (view source) (protected) Template:arm (edit) Template:cavium (edit) Template:cavium title (edit) Template:comma2 (edit) Template:comp table count (edit) Template:comp table end (edit) Template:comp table header (edit) Template:comp table start (edit) Template:ic family (edit) Template:intel (view source) (protected) Template:link-arm (edit) Template:link-cavium (edit) Template:link-intel (view source) (protected) Template:link-qualcomm (edit) Template:proc table 3 (view source) (protected) Template:qualcomm (edit) Template:see also (edit) Template:url parse anchor (view source) (protected) Template:url parse article (view source) (protected) Module:comptable (view source)

designer	Cavium +
first announced	May 30, 2016 +
first launched	May 7, 2018 +
full page name	cavium/thunderx2 +
instance of	microprocessor family +
instruction set architecture	ARMv8.1 +
main designer	Cavium +
manufacturer	TSMC +
microarchitecture	ThunderX2 + and Vulcan +
name	ThunderX2 +
process	14 nm (0.014 μm, 1.4e-5 mm) + and 16 nm (0.016 μm, 1.6e-5 mm) +
technology	CMOS +
word size	64 bit (8 octets, 16 nibbles) +