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Information for "arm holdings/microarchitectures/poseidon"

Basic information

Display titlePoseidon - Microarchitectures - ARM
Default sort keyPoseidon, ARM Holdings
Page length (in bytes)4,972
Page ID32215
Page content languageEnglish (en)
Page content modelwikitext
Indexing by robotsAllowed
Number of redirects to this page0
Counted as a content pageYes
Number of subpages of this page0 (0 redirects; 0 non-redirects)

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Edit history

Page creatorDavid (talk | contribs)
Date of page creation02:17, 14 December 2018
Latest editor95.24.51.108 (talk)
Date of latest edit22:00, 23 March 2025
Total number of edits9
Total number of distinct authors3
Recent number of edits (within past 90 days)0
Recent number of distinct authors0

Page properties

Transcluded templates (16)

Templates used on this page:

codenameNeoverse V3 +
designerARM Holdings +
first launched2023 +
full page namearm holdings/microarchitectures/poseidon +
instance ofmicroarchitecture +
instruction set architectureARMv9.0-A +
manufacturerTSMC +
microarchitecture typeCPU +
nameNeoverse V3 +
process5 nm (0.005 μm, 5.0e-6 mm) + and 4 nm (0.004 μm, 4.0e-6 mm) +