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Information for "arm holdings/microarchitectures/cortex-m55"
Basic information
| Display title | Cortex-M55 - Microarchitectures - ARM |
| Default sort key | Cortex-M55, ARM Holdings |
| Page length (in bytes) | 12,725 |
| Page ID | 35906 |
| Page content language | English (en) |
| Page content model | wikitext |
| Indexing by robots | Allowed |
| Number of redirects to this page | 0 |
| Counted as a content page | Yes |
| Number of subpages of this page | 0 (0 redirects; 0 non-redirects) |
Page protection
| Edit | Allow all users (infinite) |
| Move | Allow all users (infinite) |
Edit history
| Page creator | David (talk | contribs) |
| Date of page creation | 23:54, 15 February 2020 |
| Latest editor | 99.95.168.248 (talk) |
| Date of latest edit | 09:51, 12 January 2021 |
| Total number of edits | 18 |
| Total number of distinct authors | 3 |
| Recent number of edits (within past 90 days) | 0 |
| Recent number of distinct authors | 0 |
Page properties
| Transcluded templates (18) | Templates used on this page:
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Facts about "Cortex-M55 - Microarchitectures - ARM"
| codename | Cortex-M55 + |
| core count | 1 +, 2 + and 4 + |
| designer | ARM Holdings + |
| first launched | February 10, 2020 + |
| full page name | arm holdings/microarchitectures/cortex-m55 + |
| instance of | microarchitecture + |
| instruction set architecture | ARMv8.1-M + |
| manufacturer | TSMC + |
| microarchitecture type | CPU + |
| name | Cortex-M55 + |
| pipeline stages (max) | 5 + |
| pipeline stages (min) | 4 + |
| process | 55 nm (0.055 μm, 5.5e-5 mm) +, 45 nm (0.045 μm, 4.5e-5 mm) +, 32 nm (0.032 μm, 3.2e-5 mm) +, 28 nm (0.028 μm, 2.8e-5 mm) +, 22 nm (0.022 μm, 2.2e-5 mm) +, 16 nm (0.016 μm, 1.6e-5 mm) +, 10 nm (0.01 μm, 1.0e-5 mm) +, 7 nm (0.007 μm, 7.0e-6 mm) + and 5 nm (0.005 μm, 5.0e-6 mm) + |