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Information for "arm holdings/microarchitectures/chaberton"
Basic information
| Display title | Chaberton - Microarchitectures - ARM |
| Default sort key | Chaberton, ARM Holdings |
| Page length (in bytes) | 2,251 |
| Page ID | 36751 |
| Page content language | English (en) |
| Page content model | wikitext |
| Indexing by robots | Allowed |
| Number of redirects to this page | 0 |
| Counted as a content page | Yes |
| Number of subpages of this page | 0 (0 redirects; 0 non-redirects) |
Page protection
| Edit | Allow all users (infinite) |
| Move | Allow all users (infinite) |
Edit history
| Page creator | David (talk | contribs) |
| Date of page creation | 13:16, 4 July 2022 |
| Latest editor | 95.24.54.111 (talk) |
| Date of latest edit | 06:58, 13 May 2025 |
| Total number of edits | 2 |
| Total number of distinct authors | 2 |
| Recent number of edits (within past 90 days) | 0 |
| Recent number of distinct authors | 0 |
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| Transcluded templates (8) | Templates used on this page:
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Facts about "Chaberton - Microarchitectures - ARM"
| codename | Cortex-A725 (Chaberton) + |
| core count | 1 +, 2 + and 4 + |
| designer | ARM Holdings + |
| first launched | 2024 + |
| full page name | arm holdings/microarchitectures/chaberton + |
| instance of | microarchitecture + |
| manufacturer | TSMC + |
| microarchitecture type | CPU + |
| name | Cortex-A725 (Chaberton) + |
| process | 7 nm (0.007 μm, 7.0e-6 mm) + and 5 nm (0.005 μm, 5.0e-6 mm) + |