Revision history of "intel/xeon d/d-2161i"

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Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.	Xeon D-2161I - Intel#package + and Xeon D-2161I - Intel#pcie +
base frequency	2,200 MHz (2.2 GHz, 2,200,000 kHz) +
bus links	4 +
bus rate	8,000 MT/s (8 GT/s, 8,000,000 kT/s) +
bus type	DMI 3.0 +
clock multiplier	22 +
core count	12 +
core name	Skylake DE +
core stepping	M1 +
designer	Intel +
die count	2 +
family	Xeon D +
first announced	February 7, 2018 +
first launched	February 7, 2018 +
full page name	intel/xeon d/d-2161i +
has advanced vector extensions	true +
has advanced vector extensions 2	true +
has advanced vector extensions 512	true +
has ecc memory support	true +
has extended page tables support	true +
has feature	Advanced Encryption Standard Instruction Set Extension +, Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Vector Extensions 512 +, Enhanced SpeedStep Technology +, Extended Page Tables +, Hyper-Threading Technology +, Identity Protection Technology +, Intel VT-d +, Intel VT-x +, Intel vPro Technology +, Memory Protection Extensions +, OS Guard +, Secure Key Technology +, Speed Shift Technology +, Transactional Synchronization Extensions +, Trusted Execution Technology + and Turbo Boost Technology 2.0 +
has intel enhanced speedstep technology	true +
has intel identity protection technology support	true +
has intel secure key technology	true +
has intel speed shift technology	true +
has intel supervisor mode execution protection	true +
has intel trusted execution technology	true +
has intel turbo boost technology 2 0	true +
has intel vpro technology	true +
has intel vt-d technology	true +
has intel vt-x technology	true +
has locked clock multiplier	true +
has second level address translation support	true +
has simultaneous multithreading	true +
has transactional synchronization extensions	true +
has x86 advanced encryption standard instruction set extension	true +
instance of	microprocessor +
is multi-chip package	true +
isa	x86-64 +
isa family	x86 +
l1$ size	768 KiB (786,432 B, 0.75 MiB) +
l1d$ description	8-way set associative +
l1d$ size	384 KiB (393,216 B, 0.375 MiB) +
l1i$ description	8-way set associative +
l1i$ size	384 KiB (393,216 B, 0.375 MiB) +
l2$ description	16-way set associative +
l2$ size	12 MiB (12,288 KiB, 12,582,912 B, 0.0117 GiB) +
l3$ description	11-way set associative +
l3$ size	16.5 MiB (16,896 KiB, 17,301,504 B, 0.0161 GiB) +
ldate	February 7, 2018 +
main image	+
manufacturer	Intel +
market segment	Embedded + and Server +
max cpu count	1 +
max hsio lanes	20 +
max memory	524,288 MiB (536,870,912 KiB, 549,755,813,888 B, 512 GiB, 0.5 TiB) +
max memory bandwidth	79.47 GiB/s (81,377.28 MiB/s, 85.33 GB/s, 85,330.263 MB/s, 0.0776 TiB/s, 0.0853 TB/s) +
max memory channels	4 +
microarchitecture	Skylake (server) +
model number	D-2161I +
name	Xeon D-2161I +
number of avx-512 execution units	1 +
package	FCBGA-2518 +
part number	FH8067303534104 +
part of	Edge Server and Cloud SKUs +
process	14 nm (0.014 μm, 1.4e-5 mm) +
release price	$ 962.00 (€ 865.80, £ 779.22, ¥ 99,403.46) +
s-spec	SR3ZN +
series	D-2000 +
smp max ways	1 +
supported memory type	DDR4-2133 +
tdp	90 W (90,000 mW, 0.121 hp, 0.09 kW) +
technology	CMOS +
thread count	24 +
turbo frequency (1 core)	3,000 MHz (3 GHz, 3,000,000 kHz) +
word size	64 bit (8 octets, 16 nibbles) +
x86/has memory protection extensions	true +

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