Revision history of "fujitsu/sparc64/sparc64 xii"

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(cur | prev) 13:39, 24 March 2019‎ David (talk | contribs)‎ m . . (3,310 bytes) (-88)‎ . . (Reverted edits by 45.33.139.147 (talk) to last revision by ChippyBot) (undo)
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(cur | prev) 15:13, 13 December 2017‎ ChippyBot (talk | contribs)‎ m . . (3,310 bytes) (+1)‎ . . (Bot: moving all {{mpu}} to {{chip}}) (undo)
(cur | prev) 17:16, 30 June 2017‎ ChippyBot (talk | contribs)‎ m . . (3,309 bytes) (0)‎ . . (Bot: corrected param) (undo)
(cur | prev) 22:53, 12 April 2017‎ At32Hz (talk | contribs)‎ . . (3,309 bytes) (+63)‎ . . (undo)
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(cur | prev) 19:33, 12 April 2017‎ David (talk | contribs)‎ . . (2,987 bytes) (0)‎ . . (undo)
(cur | prev) 19:32, 12 April 2017‎ David (talk | contribs)‎ . . (2,987 bytes) (+2,987)‎ . . (Created page with "{{fujitsu title|SPARC64 XII}} {{mpu | name = SPARC64 XII | no image = Yes | image = | image size = | caption =...")

base frequency	4,250 MHz (4.25 GHz, 4,250,000 kHz) +
core count	12 +
designer	Fujitsu +
family	SPARC64 +
first announced	2015 +
first launched	April 4, 2017 +
full page name	fujitsu/sparc64/sparc64 xii +
instance of	microprocessor +
isa	SPARC V9 +
isa family	SPARC +
ldate	April 4, 2017 +
main image	+
main image caption	SPARC64 XII Chip +
manufacturer	TSMC +
market segment	Server +
max cpu count	32 +
max memory	2,097,152 MiB (2,147,483,648 KiB, 2,199,023,255,552 B, 2,048 GiB, 2 TiB) +
microarchitecture	SPARC64 XII +
model number	SPARC64 XII +
name	SPARC64 XII +
process	20 nm (0.02 μm, 2.0e-5 mm) +
smp max ways	32 +
technology	CMOS +
thread count	96 +
word size	64 bit (8 octets, 16 nibbles) +

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