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codenameNeoverse V3 +
designerARM Holdings +
first launched2023 +
full page namearm holdings/microarchitectures/poseidon +
instance ofmicroarchitecture +
instruction set architectureARMv9.0-A +
manufacturerTSMC +
microarchitecture typeCPU +
nameNeoverse V3 +
process5 nm (0.005 μm, 5.0e-6 mm) + and 4 nm (0.004 μm, 4.0e-6 mm) +