Revision history of "amd/microarchitectures/zen 4"

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(cur | prev) 22:52, 2 March 2025‎ 95.24.54.66 (talk)‎ . . (13,669 bytes) (+326)‎ . . (fixed) (undo)
(cur | prev) 18:28, 13 November 2023‎ 37.201.198.27 (talk)‎ . . (13,343 bytes) (+1)‎ . . (6.75k is not 6750, increase from 4096=8*8*2^6 to 6912=9*12*2^6 (=4096*9/8 +50%)) (undo)
(cur | prev) 11:12, 18 September 2023‎ 46.102.196.222 (talk)‎ . . (13,342 bytes) (+17)‎ . . (List Siena in the zen4c variant table) (undo)
(cur | prev) 11:03, 18 September 2023‎ 46.102.196.222 (talk)‎ . . (13,325 bytes) (+70)‎ . . (Add Siena model number) (undo)
(cur | prev) 11:34, 4 August 2023‎ 213.175.37.10 (talk)‎ . . (13,255 bytes) (+179)‎ . . (→‎Key changes from {{\\|Zen 3}}) (undo)
(cur | prev) 10:07, 25 July 2023‎ 68.102.45.173 (talk)‎ . . (13,076 bytes) (+4)‎ . . (→‎New Instructions) (undo)
(cur | prev) 12:08, 17 July 2023‎ 213.175.37.10 (talk)‎ . . (13,072 bytes) (0)‎ . . (→‎Architecture) (undo)
(cur | prev) 11:53, 17 July 2023‎ 213.175.37.10 (talk)‎ . . (13,072 bytes) (+413)‎ . . (→‎Architecture) (undo)
(cur | prev) 01:24, 17 May 2023‎ QuietRub (talk | contribs)‎ . . (12,659 bytes) (+2,560)‎ . . (Missing data, fixes, cleanup.) (undo)
(cur | prev) 13:01, 17 November 2022‎ 156.98.46.114 (talk)‎ . . (10,099 bytes) (+191)‎ . . (Added press release link for Zen 4.) (undo)
(cur | prev) 00:06, 5 November 2022‎ 23.81.176.223 (talk)‎ . . (9,908 bytes) (-2)‎ . . (Removed parenthesis on Bergamo thread count) (undo)
(cur | prev) 00:06, 5 November 2022‎ 23.81.176.223 (talk)‎ . . (9,910 bytes) (-1)‎ . . (Updated Bergamo thread count) (undo)
(cur | prev) 21:26, 9 October 2022‎ David (talk | contribs)‎ . . (9,911 bytes) (+785)‎ . . (undo)
(cur | prev) 15:32, 26 September 2022‎ Atomsymbol (talk | contribs)‎ . . (9,126 bytes) (+65)‎ . . (→‎Key changes from {{\\|Zen 3}}: Add a line about iGPU) (undo)
(cur | prev) 15:19, 26 September 2022‎ Atomsymbol (talk | contribs)‎ . . (9,061 bytes) (+91)‎ . . (→‎System DRAM: Add Raphael DDR5 memory speed (JEDEC)) (undo)
(cur | prev) 15:07, 26 September 2022‎ Atomsymbol (talk | contribs)‎ . . (8,970 bytes) (+142)‎ . . (→‎Key changes from {{\\|Zen 3}}: Add reg file sizes, ROB size) (undo)
(cur | prev) 14:57, 26 September 2022‎ Atomsymbol (talk | contribs)‎ . . (8,828 bytes) (0)‎ . . (→‎Data and Instruction Caches: Update µop cache sizes) (undo)
(cur | prev) 11:16, 1 September 2022‎ 23.81.176.148 (talk)‎ . . (8,828 bytes) (-1)‎ . . (Updated Bergamo family number) (undo)
(cur | prev) 10:09, 30 August 2022‎ 23.81.176.152 (talk)‎ . . (8,829 bytes) (+2)‎ . . (Updated L2 and L3 cache latencies) (undo)
(cur | prev) 00:12, 30 August 2022‎ 23.81.176.184 (talk)‎ . . (8,827 bytes) (+1)‎ . . (Corrected a spacing mistake.) (undo)
(cur | prev) 12:25, 29 August 2022‎ Atomsymbol (talk | contribs)‎ . . (8,826 bytes) (+266)‎ . . (Add two pieces of information from Angstronomics' Ryzen 7000 Preview) (undo)
(cur | prev) 16:46, 11 August 2022‎ 23.81.176.152 (talk)‎ . . (8,560 bytes) (0)‎ . . (EPYC DDR5-5200 to DDR5-5600) (undo)
(cur | prev) 00:20, 31 July 2022‎ 23.81.176.117 (talk)‎ . . (8,560 bytes) (+4)‎ . . (Changed Phoenix to Phoenix Point and removed the ? marks) (undo)
(cur | prev) 14:39, 26 July 2022‎ 23.81.176.120 (talk)‎ . . (8,556 bytes) (0)‎ . . (Updated EPYC Genoa number to 9004 in the "Key Changes" section) (undo)
(cur | prev) 16:42, 20 July 2022‎ 23.81.176.120 (talk)‎ . . (8,556 bytes) (0)‎ . . (Updated Genoa number scheme) (undo)
(cur | prev) 16:38, 20 July 2022‎ 23.81.176.120 (talk)‎ . . (8,556 bytes) (+7)‎ . . (Updated Genoa number scheme and guesstimated Bergamo number scheme) (undo)
(cur | prev) 00:46, 26 May 2022‎ 23.81.176.120 (talk)‎ . . (8,549 bytes) (+1)‎ . . (Updated Raphael core count with a "?") (undo)
(cur | prev) 14:59, 22 May 2022‎ 23.81.176.120 (talk)‎ . . (8,548 bytes) (-35)‎ . . (Updated Bergamo info) (undo)
(cur | prev) 09:29, 19 May 2022‎ 23.81.176.122 (talk)‎ . . (8,583 bytes) (+4)‎ . . (Info correction) (undo)
(cur | prev) 09:28, 19 May 2022‎ 23.81.176.122 (talk)‎ . . (8,579 bytes) (0)‎ . . (Corrected spelling error) (undo)
(cur | prev) 09:27, 19 May 2022‎ 23.81.176.122 (talk)‎ . . (8,579 bytes) (+29)‎ . . (Added SP6 socket) (undo)
(cur | prev) 02:19, 19 May 2022‎ 23.81.176.122 (talk)‎ . . (8,550 bytes) (0)‎ . . (Corrected Bergamo info) (undo)
(cur | prev) 02:18, 19 May 2022‎ 23.81.176.122 (talk)‎ . . (8,550 bytes) (+20)‎ . . (Updated Bergamo info) (undo)
(cur | prev) 11:54, 18 May 2022‎ 23.81.176.122 (talk)‎ . . (8,530 bytes) (-3)‎ . . (Fixed spelling error) (undo)
(cur | prev) 11:53, 18 May 2022‎ 23.81.176.122 (talk)‎ . . (8,533 bytes) (+47)‎ . . (Added more information) (undo)
(cur | prev) 02:58, 18 May 2022‎ 23.81.176.122 (talk)‎ . . (8,486 bytes) (+23)‎ . . (Added additional information) (undo)
(cur | prev) 02:53, 18 May 2022‎ 23.81.176.122 (talk)‎ . . (8,463 bytes) (+4)‎ . . (Added 6nm to Process) (undo)
(cur | prev) 01:24, 17 May 2022‎ 98.208.83.117 (talk)‎ . . (8,459 bytes) (+5)‎ . . (Added "EPYC" to Bergamo entry) (undo)
(cur | prev) 21:52, 16 May 2022‎ 98.208.83.117 (talk)‎ . . (8,454 bytes) (+225)‎ . . (Further corrections) (undo)
(cur | prev) 21:44, 16 May 2022‎ 98.208.83.117 (talk)‎ . . (8,229 bytes) (+28)‎ . . (Correcting CPU family names) (undo)
(cur | prev) 11:31, 16 May 2022‎ 98.208.83.117 (talk)‎ . . (8,201 bytes) (+1)‎ . . (Corrected Warhol to Raphael) (undo)
(cur | prev) 15:06, 23 April 2022‎ QuietRub (talk | contribs)‎ . . (8,200 bytes) (+5,891)‎ . . (undo)
(cur | prev) 08:07, 23 January 2022‎ 24.52.91.178 (talk)‎ . . (2,309 bytes) (+38)‎ . . (→‎Key changes from {{\\|Zen 3}}: improved grammar) (undo)
(cur | prev) 18:43, 8 January 2022‎ 50.4.53.206 (talk)‎ . . (2,271 bytes) (-61)‎ . . (→‎Key changes from {{\\|Zen 3}}: CES announcements) (undo)
(cur | prev) 18:39, 8 January 2022‎ 50.4.53.206 (talk)‎ . . (2,332 bytes) (+44)‎ . . (undo)
(cur | prev) 12:59, 9 November 2021‎ 61.218.132.40 (talk)‎ . . (2,288 bytes) (+41)‎ . . (undo)
(cur | prev) 12:54, 9 November 2021‎ 61.218.132.40 (talk)‎ . . (2,247 bytes) (0)‎ . . (undo)
(cur | prev) 12:53, 9 November 2021‎ 61.218.132.40 (talk)‎ . . (2,247 bytes) (0)‎ . . (undo)
(cur | prev) 12:53, 9 November 2021‎ 61.218.132.40 (talk)‎ . . (2,247 bytes) (+127)‎ . . (undo)
(cur | prev) 12:47, 9 November 2021‎ 61.218.132.40 (talk)‎ . . (2,120 bytes) (+22)‎ . . (undo)

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codename	Zen 4 +
core count	96 +, 64 +, 48 +, 32 +, 28 +, 24 +, 16 +, 12 +, 8 + and 6 +
designer	AMD +
first launched	September 2022 +
full page name	amd/microarchitectures/zen 4 +
instance of	microarchitecture +
manufacturer	TSMC +
microarchitecture type	CPU +
name	Zen 4 +
process	5 nm (0.005 μm, 5.0e-6 mm) + and 6 nm (0.006 μm, 6.0e-6 mm) +

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