Editing hisilicon/microarchitectures/taishan v110

{{hisilicon title|TaiShan|arch}}
{{microarchitecture
|atype=CPU
|name=TaiShan
|designer=HiSilicon
|manufacturer=TSMC
|introduction=2019
|process=7 nm
|cores=32
|cores 2=48
|cores 3=64
|type=Superscalar
|type 2=Superpipeline
|oooe=Yes
|speculative=Yes
|renaming=Yes
|decode=4-way
|isa=ARMv8.2-A
|feature=Hardware compression accelerator
|feature 2=Hardware cryptography accelerator
|extension=NEON
|l1i=64 KiB
|l1i per=core
|l1d=64 KiB
|l1d per=core
|l2=512 KiB
|l2 per=core
|l3=1 MiB
|l3 per=core
|core name=TaiShan
}}
'''TaiShan''' is a high-performance [[ARM]] server microarchitecture designed by [[HiSilicon]] for [[Huawei]]'s own TaiShan servers.

== Brands ==
TaiShan-based CPUs are branded as the {{hisilicon|hi16xx#920_Series|Kunpeng 920 series}}.

== Release Dates ==
Kunpeng 920 CPUs were officially launched in early 2019.

== Architecture ==
* [[TSMC]] [[7 nm|7 nm HPC process]]
{{expand list}}

=== Block Diagram ===
==== Entire Chip ====
:[[File:taishan soc block diagram.svg|900px]]

=== Memory Hierarchy ===
* Cache
** L1I Cache
*** 64 KiB/core, private
** L1D Cache
*** 64 KiB/core, private
** L2 Cache
*** 512 KiB/core, private
** L3 Cache
*** 1 MiB/core
*** Shared by all cores
** System DRAM
*** 1 TiB Max Memory / socket
*** 8 Channels
*** DDR4, up to 2933 MT/s
**** 1 DPC and 2 DPC support
*** 8 B/cycle/channel (@ memory clock)
*** ECC, SDDC, DDDC

== Overview ==
{{empty section}}

== Core ==
{{empty section}}

== Scalability ==
There are three cache coherent ports on each SoC. Every port supports 240 Gb/s (30 GB/s) of peak bandwidth for a total aggregated bandwidth of 720 Gb/s (90 GB/s) in a 2-way [[symmetric multiprocessing]] configuration.

:[[File:Kunpeng 920 2smp.svg|600px]]

With all three links, there is also support for 4-way SMP. In this configuration, one link from each socket is connected to another socket for an all-for-all connection.


:[[File:Kunpeng 920 4smp.svg|600px]]

== Die ==
* TSMC [[7 nm|7 nm HPC]]
* 20,000,000,000 transistors

== All TaiShan Chips ==
{{empty section}}

== Bibliography ==
* Huawei. ''Personal Communication''. 2019
* Huawei Connect 2018. October 2018
* HiSilicon Event. January 7, 2019
codename	TaiShan v110 +
core count	32 +, 48 + and 64 +
designer	HiSilicon +
first launched	2019 +
full page name	hisilicon/microarchitectures/taishan v110 +
instance of	microarchitecture +
instruction set architecture	ARMv8.2-A +
manufacturer	TSMC +
microarchitecture type	CPU +
name	TaiShan v110 +
process	7 nm (0.007 μm, 7.0e-6 mm) +