Editing nvidia/tegra/xavier

{{nvidia title|Tegra Xavier}}
{{chip
|name=Xavier
|image=xavier soc chip.png
|designer=Nvidia
|manufacturer=TSMC
|model number=Tegra194
|market=Artificial Intelligence
|market 2=Embedded
|first announced=January 8, 2018
|first launched=June, 2018
|family=Tegra
|isa=ARMv8
|isa family=ARM
|microarch=Carmel
|microarch 2=Volta
|process=12 nm
|transistors=9,000,000,000
|technology=CMOS
|die area=350 mm²
|word size=64 bit
|core count=8
|thread count=8
|tdp=30 W
|tdp typical=20 W
}}
'''Tegra Xavier''' is a {{arch|64}} [[ARM]] high-performance system on a chip for autonomous machines designed by [[Nvidia]] and introduced in [[2018]]. Xavier is incorporated into a number of [[Nvidia]]'s computers including the Jetson Xavier, Drive Xavier, and the Drive Pegasus.

== Overview ==
[[File:xavier overview.png|right|thumb|Overview (HC 30)]]
Xavier is an autonomous machine process designed by [[Nvidia]] and introduced at CES 2018. Silicon came back in the last week of December 2017 with sampling started in the first quarter of 2018. NVIDIA plans on mass production by the end of the year. NVIDIA reported that the product is a result of $2 billion R&D and 8,000 engineering years. The chip is said to have full redundancy and diversity in its functional blocks.

:[[File:xavier block.svg|500px]]

The design targets and architecture started back in [[2014]]. The chip itself comprises an eight-core CPU cluster, GPU, [[neural processor|deep learning accelerator]], vision accelerator, ISP, and a set of multimedia accelerators. Xavier features a large set of I/O and has been designed for safety and reliability supporting various standards such as Functional safety [[ISO-26262]] and [[ASIL]] level C. The CPU cluster is fully [[cache coherent]] and the coherency is extended to all the other [[accelerators]] on-chip.

== Architecture ==
=== CPU ===
{{main|nvidia/microarchitectures/carmel|l1=Carmel core}}
The chip features eight control/management {{nvidia|Carmel|l=arch}} cores, Nvidia's own custom {{arch|64}} [[ARM]] cores. Those cores implement [[ARMv8.2]] with [[RAS]] support and safety built-in, including dual-execution mode. All cores are fully [[cache coherent]] which is extended to {{nvidia|Volta|the GPU|l=arch}} and all the other accelerators in the chip.

=== GPU ===
{{main|nvidia/microarchitectures/volta|l1=Volta}}
The chip incorporates a {{nvidia|Volta|l=arch}} GPU with 512 {{nvidia|CUDA Cores}} capable of operating in 64-bit and 32-bit floating point as well as 8-bit integer. This allows the various [[deep learning]] [[artificial neural networks]] types to run efficiently in the format most suitable for them. This translates to 1.3 CUDA TOPS (32-bit FP) and another 20 Tensor Core TOPS (16-bit FP).

=== Accelerators ===
Xavier incorporates a Programmable Vision Accelerator (PVA) for processing computer vision. It is capable of 1.6 [[TOPS]] and the ability to do [[stereo disparity]] (e.g., processing parallax between two cameras to obtain useful information such as depth), optical flow (e.g., direction and speed of vectors), and image processing. Additionally, since the chip is expected to be connected to a network of cameras (e.g., side, front, inside), the chip is capable of doing real-time [[encoding]] for all camera in [[high dynamic range]]. 

{| class="wikitable"
|-
! colspan="2" | Video Processing
|-
! Encode !! Decode
|-
| 1.2 GPIX/s || 1.8 GPIX/s
|}

The chip has an [[ISP]] with native full-range [[HDR]] support and [[tile rendering]] capable of processing at 1.5 GPIX/s.

==== Deep Learning Accelerator ====
The chip incorporates a deep learning accelerator (DLA) that implements a number of specific set of deep learning functions common to many applications. This allows them to read the highest possible energy efficiency for those operations. The DLA has a peak performance of 5 [[TOPS]] for 16-bit integers or 10 [[TOPS]] for 8-bit integer.

== Memory controller ==
{{memory controller
|type=LPDDR4X-4266
|ecc=Yes
|channels=8
|width=32 bit
|max bandwidth=127.1 GiB/s
}}

== I/O ==
* 16 [[Camera Serial Interface|CSI]] channels
** 109 Gbps total bandwidth
* 1x gE interface
* 1x 10gE interface

== Die ==
=== SoC ===
* 9,000,000,000 transistors
* 350 mm² die size
* [[TSMC]]'s [[12FFN]]

[[File:nvidia xavier die shot.png|900px]]


[[File:nvidia xavier die shot (annotated).png|900px]]

=== GPU ===
* ~89.2 mm² silicon area

:[[File:xavier die volta gpu.png|500px]]


:[[File:xavier die volta gpu (annotated).png|500px]]

=== CPU ===
See {{nvidia|carmel#CPU_Complex_2|Carmel § CPU Complex|l=arch}}.

=== PVA ===
:[[File:xavier die pva.png|650px]]

:[[File:xavier die pva (annotated).png|650px]]

=== MM Engine / DLA ===
* ~21.75 mm² silicon area

:[[File:xavier die mm-dl accel.png|650px]]

== Borads ==
<gallery mode=packed-hover heights="300px" widths="300px">
jetson_xavier_(front).png|Jetson Xavier, front
jetson_xavier_(back).png|Jetson Xavier, back
</gallery>

== Documents ==
* [[:File:ces2018 - nvidia drive xavier.pdf|CES 2018: Nvidia Drive Xavier]]

== Bibliography ==
* IEEE Hot Chips 30 Symposium (HCS) 2018.
core count	8 +
core name	Carmel +
designer	Nvidia +
die area	350 mm² (0.543 in², 3.5 cm², 350,000,000 µm²) +
family	Tegra +
first announced	January 8, 2018 +
first launched	June 2018 +
full page name	nvidia/tegra/xavier +
has ecc memory support	true +
instance of	microprocessor +
isa	ARMv8 +
isa family	ARM +
ldate	June 2018 +
main image	+
manufacturer	TSMC +
market segment	Artificial Intelligence + and Embedded +
max cpu count	4 +
max memory bandwidth	127.1 GiB/s (130,150.4 MiB/s, 136.473 GB/s, 136,472.586 MB/s, 0.124 TiB/s, 0.136 TB/s) +
max memory channels	8 +
microarchitecture	Carmel + and Volta +
model number	Tegra194 +
name	Xavier +
process	12 nm (0.012 μm, 1.2e-5 mm) +
smp max ways	4 +
supported memory type	LPDDR4X-4266 +
tdp	30 W (30,000 mW, 0.0402 hp, 0.03 kW) +
tdp (typical)	20 W (20,000 mW, 0.0268 hp, 0.02 kW) +
technology	CMOS +
thread count	8 +
transistor count	9,000,000,000 +
word size	64 bit (8 octets, 16 nibbles) +