Editing intel/atom/c3955

{{intel title|Atom C3955}}
{{mpu
|name=Atom C3955
|image=denverton (front).png
|designer=Intel
|manufacturer=Intel
|model number=C3955
|part number=HW8076503528301
|s-spec=SR3F3
|market=Server
|market 2=Embedded
|first announced=August 15, 2017
|first launched=August 15, 2017
|release price=$434.00
|family=Atom
|series=3000
|locked=Yes
|frequency=2,100 MHz
|turbo frequency1=2,400 MHz
|clock multiplier=21
|isa=x86-64
|isa family=x86
|microarch=Goldmont
|core name=Denverton
|core family=6
|core stepping=B1
|process=14 nm
|technology=CMOS
|word size=64 bit
|core count=16
|thread count=16
|max cpus=1
|max memory=256 GiB
|tdp=32 W
|tjunc min=0 °C
|tjunc max=100 °C
|tcase min=0 °C
|tcase max=78 °C
|tstorage min=-25 °C
|tstorage max=125 °C
|package module 1={{packages/intel/fcbga-1310}}
}}
'''Atom C3955''' is a {{arch|64}} [[hexadeca-core]] ultra-low power [[x86]] microserver [[system on a chip]] introduced by [[Intel]] in 2017. The C3955, which is manufactured on a [[14 nm process]], is based on the {{intel|Goldmont|l=arch}} microarchitecture. This chip operates at 2.1 GHz with a [[TDP]] of 32 W and a {{intel|turbo boost}} frequency of up to 2.4 GHz. The C3955 supports up to a dual-channel of 256 GiB of DDR4-2400 [[ECC]] memory. This model is part of {{intel|Denverton|l=core}}'s [[part of::Server and Cloud Storage SKUs]].

== Cache ==
{{main|intel/microarchitectures/goldmont#Memory_Hierarchy|l1=Goldmont § Cache}}
{{cache size
|l1 cache=896 KiB
|l1i cache=512 KiB
|l1i break=16x32 KiB
|l1i desc=8-way set associative
|l1i policy=write-back
|l1d cache=384 KiB
|l1d break=16x24 KiB
|l1d desc=6-way set associative
|l1d policy=write-back
|l2 cache=16 MiB
|l2 break=8x2 MiB
|l2 desc=16-way set associative
|l2 policy=write-back
}}

== Memory controller ==
{{memory controller
|type=DDR3L-1600
|type 2=DDR4-2400
|ecc=Yes
|max mem=256 GiB
|controllers=1
|channels=2
|max bandwidth=35.76 GiB/s
|bandwidth schan=17.88 GiB/s
|bandwidth dchan=35.76 GiB/s
}}

== Expansions ==
This chip incorporates 20 high-speed I/O (HSIO) lanes that may be configured as any combination of the following:
{{expansions main
|
{{expansions entry
|type=PCIe
|pcie revision=3.0
|pcie lanes=20
|pcie config=x8
|pcie config 2=x4
|pcie config 3=x2
}}
{{expansions entry
|type=USB
|usb revision=3.0
|usb ports=8
}}
}}

== Features == 
{{x86 features
|real=Yes
|protected=Yes
|smm=Yes
|fpu=Yes
|x8616=Yes
|x8632=Yes
|x8664=Yes
|nx=Yes
|mmx=Yes
|emmx=Yes
|sse=Yes
|sse2=Yes
|sse3=Yes
|ssse3=Yes
|sse41=Yes
|sse42=Yes
|sse4a=No
|avx=No
|avx2=No
|avx512f=No
|avx512cd=No
|avx512er=No
|avx512pf=No
|avx512bw=No
|avx512dq=No
|avx512vl=No
|avx512ifma=No
|avx512vbmi=No
|avx5124fmaps=No
|avx5124vnniw=No
|avx512vpopcntdq=No
|abm=No
|tbm=No
|bmi1=No
|bmi2=No
|fma3=No
|fma4=No
|aes=Yes
|rdrand=Yes
|sha=Yes
|xop=No
|adx=No
|clmul=No
|f16c=No
|tbt1=No
|tbt2=Yes
|tbmt3=No
|bpt=No
|eist=Yes
|sst=No
|flex=No
|fastmem=No
|ivmd=No
|intelnodecontroller=No
|intelnode=No
|kpt=No
|ptt=No
|intelrunsure=No
|mbe=No
|isrt=No
|sba=No
|mwt=No
|sipp=No
|att=No
|ipt=No
|tsx=No
|txt=No
|ht=No
|vpro=No
|vtx=Yes
|vtd=Yes
|ept=Yes
|mpx=Yes
|sgx=No
|securekey=No
|osguard=No
|3dnow=No
|e3dnow=No
|smartmp=No
|powernow=No
|amdvi=No
|amdv=No
|amdsme=No
|amdtsme=No
|amdsev=No
|rvi=No
|smt=No
|sensemi=No
|xfr=No
}}
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.	Atom C3955 - Intel#package + and Atom C3955 - Intel#pcie +
base frequency	2,100 MHz (2.1 GHz, 2,100,000 kHz) +
clock multiplier	21 +
core count	16 +
core family	6 +
core model	95 +
core name	Denverton +
core stepping	B1 +
designer	Intel +
family	Atom +
first announced	August 15, 2017 +
first launched	August 15, 2017 +
full page name	intel/atom/c3955 +
has ecc memory support	true +
has extended page tables support	true +
has feature	Advanced Encryption Standard Instruction Set Extension +, Enhanced SpeedStep Technology +, Intel VT-x +, Intel VT-d +, Turbo Boost Technology 2.0 +, Extended Page Tables + and Memory Protection Extensions +
has intel enhanced speedstep technology	true +
has intel turbo boost technology 2 0	true +
has intel vt-d technology	true +
has intel vt-x technology	true +
has locked clock multiplier	true +
has second level address translation support	true +
has x86 advanced encryption standard instruction set extension	true +
instance of	microprocessor +
isa	x86-64 +
isa family	x86 +
l1$ size	896 KiB (917,504 B, 0.875 MiB) +
l1d$ description	6-way set associative +
l1d$ size	384 KiB (393,216 B, 0.375 MiB) +
l1i$ description	8-way set associative +
l1i$ size	512 KiB (524,288 B, 0.5 MiB) +
l2$ description	16-way set associative +
l2$ size	16 MiB (16,384 KiB, 16,777,216 B, 0.0156 GiB) +
ldate	August 15, 2017 +
main image	+
manufacturer	Intel +
market segment	Server + and Embedded +
max case temperature	351.15 K (78 °C, 172.4 °F, 632.07 °R) +
max cpu count	1 +
max hsio lanes	20 +
max junction temperature	373.15 K (100 °C, 212 °F, 671.67 °R) +
max memory	262,144 MiB (268,435,456 KiB, 274,877,906,944 B, 256 GiB, 0.25 TiB) +
max memory bandwidth	35.76 GiB/s (36,618.24 MiB/s, 38.397 GB/s, 38,397.008 MB/s, 0.0349 TiB/s, 0.0384 TB/s) +
max memory channels	2 +
max storage temperature	398.15 K (125 °C, 257 °F, 716.67 °R) +
max usb ports	8 +
microarchitecture	Goldmont +
min case temperature	273.15 K (0 °C, 32 °F, 491.67 °R) +
min junction temperature	273.15 K (0 °C, 32 °F, 491.67 °R) +
min storage temperature	248.15 K (-25 °C, -13 °F, 446.67 °R) +
model number	C3955 +
name	Atom C3955 +
package	FCBGA-1310 +
part number	HW8076503528301 +
part of	Server and Cloud Storage SKUs +
process	14 nm (0.014 μm, 1.4e-5 mm) +
release price	$ 434.00 (€ 390.60, £ 351.54, ¥ 44,845.22) +
s-spec	SR3F3 +
series	3000 +
smp max ways	1 +
supported memory type	DDR3L-1600 + and DDR4-2400 +
tdp	32 W (32,000 mW, 0.0429 hp, 0.032 kW) +
technology	CMOS +
thread count	16 +
turbo frequency (1 core)	2,400 MHz (2.4 GHz, 2,400,000 kHz) +
word size	64 bit (8 octets, 16 nibbles) +
x86/has memory protection extensions	true +