Editing marvell/armada/610

{{marvell title|ARMADA 610}}
'''ARMADA 610''' was a {{arch|32}} [[ARM]] microprocessor introduced by [[Marvell]] in 2009. This processor, which is based on Marvell's {{marvell|Sheeva PJ4|l=arch}} microarchitecture, operated at 1 GHz and supported up to DDR3-1066 memory.

== Cache ==
{{main|intel/microarchitectures/sheeva pj4#Memory_Hierarchy|l1=Sheeva PJ4 § Cache}}
{{cache size
|l1 cache=64 KiB
|l1i cache=32 KiB
|l1i break=1x32 KiB
|l1d cache=32 KiB
|l1d break=1x32 KiB
|l2 cache=256 KiB
|l2 break=1x256 KiB
}}

== Memory controller ==
{{memory controller
|type=DDR3-1066
|type 2=DDR2-800
|ecc=No
|max mem=64 GiB
|controllers=1
|channels=1
|max bandwidth=7.942 GiB/s
|bandwidth schan=7.942 GiB/s
}}

=== Static Memory Controller ===
* 4 chip selects, up to 256 MB each
*  Asynch/Sync operation up to 78 MHz
* A/D and AA/D Mode, x8 & x16 NOR Flash interface
* Support for VLIO or companion chips 

===NAND Flash Controller===
* ONFI compliant controller supporting SLC and MLC NAND, x8 & x16, small block and large block
* 2 Chip Selects with up to 64GB of address space
* Support for 2 KB and 4 KB page sizes
* 2-bit detect/1-bit correct ECC & 16-bit correct BCH 

=== MMC, SD and SDIO Controller===
* 4x MMC/SD/SDIO/CE-ATA Controllers
* Supports MMC/eMMC v4.2, 4.3 and 4.4
* SDIO v 2.0, SDcard v2.1 and v3.0 (UHS-I)
* CE-ATA 1/4/8-Bit, SPI mode and boot suppor

== Expansions ==
{{expansions
|usb revision=2.0
|usb ports=3
|usb extra=2x HSIC, 1x FSIC/12pin ULPI
|uart=Yes
|uart ports=4
|jtag=Yes
|i2c=Yes
|i2c ports=6
}}

== Graphics ==
This chip has a custom integrated [[GPU]] capable of 45 million triangle strips per second, 250 Mpixel/s fill rate and offer full support for OpenGL ES 2.0 and 1.1 and Open VG 1.1.

* Integrated video accelerator supporting 30 fps 1080p decode and encode
* 1080p decode support for H.264 high profile, VC-1/WMV, MPEG-4, MPEG-2, H.263, On-2.
* 1080p encode support for h.264 high profile, MPEG-4, MPEG-2, H.263 and On-2

== Hardware Accelerators ==
=== Marvell Wireless Trusted Module v3 ===
* Hashing units: MD5, SHA-1, HMAC-SHA-1; SHA-224/SHA256 and HMAC, SHA-512 and HMAC, MD5 and HMAC-MD5
* Symmetric crypto: AES (128 to 256 & ECB, CBC, CTR/XTS modes), DES/3DES (ECB & CBC), RC4
* Asymmetric crypto: ECC (Prime field ECC, FIPS std curve EC-224/256, EC-DSA) & RSA (RSA key gen, PKCS#1 v1.5/v2.1 Digital Signatures, x.509 Digital Certificate), & DiffieHellman Key exchange. True HW RNG, FIPS 140-2 certification
base frequency	1,000 MHz (1 GHz, 1,000,000 kHz) +
core count	1 +
core name	Sheeva PJ4 +
designer	Marvell +
family	ARMADA 600 +
first announced	October 19, 2009 +
first launched	January 5, 2010 +
full page name	marvell/armada/610 +
has ecc memory support	false +
instance of	microprocessor +
integrated gpu	GC860 +
integrated gpu designer	Vivante +
io voltage	1.5 V (15 dV, 150 cV, 1,500 mV) +, 3 V (30 dV, 300 cV, 3,000 mV) + and 3.3 V (33 dV, 330 cV, 3,300 mV) +
io voltage tolerance	0.3 V +
isa	ARMv5 + and ARMv6 +
isa family	ARM +
l1$ size	64 KiB (65,536 B, 0.0625 MiB) +
l1d$ size	32 KiB (32,768 B, 0.0313 MiB) +
l1i$ size	32 KiB (32,768 B, 0.0313 MiB) +
l2$ size	0.25 MiB (256 KiB, 262,144 B, 2.441406e-4 GiB) +
ldate	January 5, 2010 +
manufacturer	TSMC +
market segment	Mobile +
max cpu count	1 +
max memory	2,048 MiB (2,097,152 KiB, 2,147,483,648 B, 2 GiB, 0.00195 TiB) +
max memory bandwidth	7.942 GiB/s (8,132.608 MiB/s, 8.528 GB/s, 8,527.658 MB/s, 0.00776 TiB/s, 0.00853 TB/s) +
max memory channels	1 +
microarchitecture	Sheeva PJ4 +
model number	610 +
name	ARMADA 610 +
part number	88AP610 +
platform	ARMADA +
process	55 nm (0.055 μm, 5.5e-5 mm) +
series	600 +
smp max ways	1 +
supported memory type	DDR2-800 + and DDR3-1066 +
thread count	1 +
word size	32 bit (4 octets, 8 nibbles) +