Editing annapurna labs/graviton/graviton4

{{annapurna title|AWS Graviton4}}
{{chip
|name=AWS Graviton4
}}
'''AWS Graviton4''' ('''Alpine ALC14C00''') is a [[hexanonaconta-core]] [[ARMv9]] multiprocessor designed by [[Amazon]] ([[Annapurna Labs]]) for Amazon's own infrastructure. Graviton4 is a [[5 nm]](?) 7-chiplet design SoC based on the Arm [[CMN-700 mesh interconnect]] and [[Neoverse V2]] core microarchitecture. This chip supports dodeca-channel DDR5-5600 ECC memory along with 96 lanes of PCIe 5.0.

== Overview ==
This 4th-generation server processor was first announced during Amazon's AWS re:Invent [[2023]] by Adam Selipsky in his keynote. The general rollout for the Graviton4 chip in the AWS data center occurred in early 2024. These processors are offered as part of Amazon's EC2 instances.

Graviton4 features a 7-chiplet design similar to its predecessor, {{\\|Graviton3}}. This chip features 96 cores, 50% more than the prior generation. The core implementation was updated to Arm's {{armh|Neoverse V2}} microarchitecture with 2x256b [[Scalable Vector Extension|SVE]] support, also bringing support up to [[Armv9.0]] ISA for the first time. The chip supports up to 12 channels for DDR5 ECC DIMMs with data rates of up to 5600 MT/s. The Graviton4 tripled the number of PCIe lanes to 96 lanes of PCIe 5.0.

The Graviton4 is the first chip from the Graviton family to feature multiprocessing support. The chip introduced dual-socket support with full coherency for up to 192 vCPUs and DDR5 channels on a single server. The Graviton4 also expanded encryption support to the new multi-socket coherency links as well as to the Nitro cards interfaces. The full platform can be configured to run in a number of modes that can potentially offer additional power saving: two non-coherent virtual systems, one coherent virtual system, two metal systems, or one metal system.

=== Packaging ===
The Graviton4 features a 7-chiplet architecture similar in design to the Graviton3. The compute SoC die sits in the middle with 4 DDR memory controller dies and 2 PCIe controller dies. Each DDR memory controller features support for 3 memory channels - two dies to the east and two dies to the west for a total of 6 memory channels on each side. There are two PCIe controller dies - one to the north and one to the south of the chip. The four DDR memory controller dies are interconnected with the SoC via embedded silicon bridges in the package.Unlike the {{\\|Graviton3}}, the two PCIe controller dies are not abutting the compute SoC die and are no longer controller via an embedded bridge in the package.

== Cache ==
{{main|arm_holdings/microarchitectures/neoverse v2#Memory_Hierarchy|l1=Neoverse V2 § Cache}}
{{cache size
|l1 cache=12 MiB
|l1i cache=6 MiB
|l1i break=96x64 KiB
|l1d cache=6 MiB
|l1d break=96x64 KiB
|l2 cache=192 MiB
|l2 break=96x2 MiB
}}

== Memory controller ==
{{memory controller
|type=DDR5-5600
|ecc=Yes
|controllers=4
|channels=12
|max bandwidth=537.6 GB/s
|bandwidth schan=44.8 GB/s
|bandwidth dchan=89.6 GB/s
|bandwidth qchan=179.2 GB/s
|bandwidth ochan=358.4 GB/s
|bandwidth 10chan=448.0 GB/s
|bandwidth 12chan=537.6 GB/s
}}

== Expansions ==
{{expansions
| pcie revision      = 5.0
| pcie lanes         = 96
| pcie config        = x16
| pcie config 2      = x8
| pcie config 3      = x4
}}
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.	AWS Graviton4 - Annapurna Labs (Amazon)#io +
core count	96 +
designer	Annapurna Labs +
die count	7 +
family	Graviton +
first announced	November 28, 2023 +
first launched	November 28, 2023 +
full page name	annapurna labs/graviton/graviton4 +
has ecc memory support	true +
instance of	microprocessor +
is multi-chip package	true +
isa	ARMv9.0-A +
isa family	ARM +
l1$ size	12,288 KiB (12,582,912 B, 12 MiB) +
l1d$ size	6,144 KiB (6,291,456 B, 6 MiB) +
l1i$ size	6,144 KiB (6,291,456 B, 6 MiB) +
l2$ size	192 MiB (196,608 KiB, 201,326,592 B, 0.188 GiB) +
ldate	November 28, 2023 +
main image	+
main image caption	Graviton4 Package Front +
manufacturer	TSMC +
market segment	Server +
max cpu count	2 +
max memory bandwidth	500.679 GiB/s (512,695.312 MiB/s, 537.6 GB/s, 537,600 MB/s, 0.489 TiB/s, 0.538 TB/s) +
max memory channels	12 +
max pcie lanes	96 +
microarchitecture	Neoverse V2 +
model number	Graviton4 +
name	AWS Graviton4 +
part number	ALC14C00 +
smp interconnect	Cache Coherent Interconnect for Accelerators (CCIX) +
smp interconnect links	3 +
smp max ways	2 +
supported memory type	DDR5-5600 +
technology	CMOS +
thread count	96 +
word size	64 bit (8 octets, 16 nibbles) +