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R-Car E2
General Info
Designer	Renesas, ARM Holdings
Manufacturer	TSMC
Model Number	E2
Part Number	R8A7794
Market	Embedded
Introduction	October 22, 2014 (announced) June, 2016 (launched)
General Specs
Family	R-Car
Series	2nd Gen
Frequency	1,000 MHz, 780 MHz
Microarchitecture
ISA	ARMv7 (ARM), SuperH (SuperH)
Microarchitecture	Cortex-A7, SH-4A
Core Name	Cortex-A7, SH-4A
Process	28 nm
Technology	CMOS
Word Size	32 bit
Cores	3
Threads	3
Max Memory	2 GiB
Multiprocessing
Max SMP	1-Way (Uniprocessor)
Electrical
Vcore	1.0 V
VI/O	3.3 V, 1.8 V
Packaging
Package FCBGA-501 (BGA) Dimension 21 mm x 21 mm Pitch 0.80 mm Ball Count 501 Interconnect BGA-501

R-Car E2 is an entry-level embedded tri-core SoC designed by Renesas for the automotive industry and introduced in late 2014. The E2 incorporates two Cortex-A7 cores operating at 1 GHz along with a SH-4A core operating at 780 MHz for real-time processing. This chip includes an Imagination PowerVR SGX540 GPU operating at 260 MHz and supports up to 2 GiB of dual-channel DDR3-1333 memory.

Cache

Main article: Cortex-A7 § Cache

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

L1$ 192 KiB 196,608 B 0.188 MiB L1I$ 96 KiB 98,304 B 0.0938 MiB 3x32 KiB     L1D$ 96 KiB 98,304 B 0.0938 MiB 3x32 KiB     L2$ 512 KiB 0.5 MiB 524,288 B 4.882812e-4 GiB     1x512 KiB

Memory controller

[Edit/Modify Memory Info]

	Integrated Memory Controller
	Max Type DDR3-1333 Supports ECC No Max Mem 2 GiB Controllers 1 Channels 2 Width 32 bit Max Bandwidth 9.93 GiB/s 10,168.32 MiB/s 10.662 GB/s 10,662.256 MB/s 0.0097 TiB/s 0.0107 TB/s Bandwidth Single 4.97 GiB/s Double 9.93 GiB/s

Expansions

• Flash ROM and SRAM, Data bus width: 8 or 16 bits
• USB 2.0 host interface × 2 ports (wPHY)
• SD host interface × 3 ch (SDXC, UHS-I)
• Multimedia card interface × 1 ch
• I²C bus interface × 8 ch
• Serial communication interface (SCIF) × 18 ch
• Quad serial peripheral interface (QSPI) × 1 ch (for boot)
• Clock-synchronized serial interface (MSIOF) × 3 ch (SPI/IIS)
• Ethernet AVB controller (IEEE802.1BA/802.1AS/802.1Qav/IEEE1722, GMII/MII, without PHY)
• Ethernet controller (IEEE802.3u, RMII, without PHY)

Graphics

[Edit/Modify IGP Info]

	Integrated Graphics Information
	GPU PowerVR SGX540 Designer Imagination Technologies Execution Units 1 Max Displays 2 Frequency 260 MHz 0.26 GHz 260,000 KHz

Features

[Edit/Modify Supported Features]

	Supported ARM Extensions & Processor Features
	Thumb-2 Thumb-2 Extension ThumbEE Thumb Execution Environment Extension VFPv4 Vector Floating Point (VFP) v4 Extension NEON Advanced SIMD extension

Block Diagram

Dev Board ("ALT")

• 210 mm x 160 mm
• 68 MB serial flash & 8 GByte eMMC memory
• 1 GB DDR3-DRAM-1333; 2 x 16-bit configuration
• RS-232C, UART, 2x USB, SD, LAN, CAN
• EtherAVB PHY Connetor
• Video in (2ch)
• RGB and LVDS display-out
• switches, LEDs, I/O expansion headers