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R-Car M1A
General Info
Designer	Renesas, ARM Holdings
Manufacturer	TSMC
Model Number	M1A
Part Number	R8A77781
Market	Embedded
Introduction	February 16, 2011 (announced) June, 2012 (launched)
Release Price	$70
General Specs
Family	R-Car
Series	1st Gen
Frequency	800 MHz
Microarchitecture
ISA	ARMv7 (ARM), SuperH (SuperH)
Microarchitecture	Cortex-A9, SH-4A
Core Name	Cortex-A9, SH-4A
Process	40 nm
Technology	CMOS
Word Size	32 bit
Cores	2
Threads	2
Max Memory	1 GiB
Electrical
Vcore	1.2 V
VI/O	3.3 V
Packaging
Package FCBGA-472 (BGA) Dimension 21 mm x 21 mm Pitch 0.80 mm Ball Count 472 Interconnect BGA-472

R-Car M1A is a mid-range performance embedded dual-core SoC for the automotive industry designed by Renesas and introduced in 2011. The M1A features a single Cortex-A9 core and an additional SH-4A core, both operating at 800 MHz. This chip incorporates Imagination's PowerVR SGX540 GPU operating at 200 MHz. This SoC supports up to 1 GiB of dual-channel DDR3-1066 memory.

Introduced early-2011 with samples available in May 2011. Renesas expected mass production to begin in June 2012.

Cache

Main article: Cortex-A9 § Cache

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

L1$ 128 KiB 131,072 B 0.125 MiB L1I$ 64 KiB 65,536 B 0.0625 MiB 2x32 KiB 4-way set associative   L1D$ 64 KiB 65,536 B 0.0625 MiB 2x32 KiB 4-way set associative

Memory controller

[Edit/Modify Memory Info]

	Integrated Memory Controller
	Max Type DDR3-1066, DDR2-800 Supports ECC No Max Mem 1 GiB Controllers 1 Channels 2 Width 32 bit Max Bandwidth 7.95 GiB/s 8,140.8 MiB/s 8.536 GB/s 8,536.248 MB/s 0.00776 TiB/s 0.00854 TB/s Bandwidth Single 3.97 GiB/s Double 7.95 GiB/s

Expansions

[Edit/Modify Expansions Info]

	Expansion Options
	USB Revision 2.0 Ports 2 Rate 480 Mbps UART Ports 8 SATA Revision 3.0 Ports 1 I²C Ports 4 GP I/O Yes JTAG Yes

• MLB (MOST150) 6-Pin I/F
• 2 x CAN 32 Message Buffers
• MMC
• 3 x SD

Graphics

• 20MPoly/s; 1000MPix/s; 3.2GFlops/s

[Edit/Modify IGP Info]

	Integrated Graphics Information
	GPU PowerVR SGX540 Designer Imagination Technologies Execution Units 2 Max Displays 2 Frequency 200 MHz 0.2 GHz 200,000 KHz Standards OpenGL 2.1 OpenGL ES 2.0

Features

[Edit/Modify Supported Features]

	Supported ARM Extensions & Processor Features
	Thumb-2 Thumb-2 Extension ThumbEE Thumb Execution Environment Extension VFPv3 Vector Floating Point (VFP) v3 Extension NEON Advanced SIMD extension Jazelle Direct Bytecode eXecution

Block Diagram

Dev Board ("MILAN")

• 165 mm x 120 mm
• R-Car M1A
• 64 MiB flash memory
• 512 MiB DDR3-DRAM
• RS-232C, UART, USB,SD, LAN, CAN, MLB interfaces
• HDMI display out (with HDMI to DVI adapter)
• switches, LEDs,I/O expansion headers