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EPYC 7551P
General Info
Designer	AMD
Manufacturer	GlobalFoundries
Model Number	7551P
Part Number	PS755PBDVIHAF
Market	Server
Introduction	June 20, 2017 (announced) June 20, 2017 (launched)
Release Price	$2,100
Shop	Amazon
General Specs
Family	EPYC
Series	7000
Locked	No
Frequency	2,000 MHz
Turbo Frequency	3,000 MHz (1 core), 3,000 MHz (2 cores), 3,000 MHz (3 cores), 3,000 MHz (4 cores), 3,000 MHz (5 cores), 3,000 MHz (6 cores), 3,000 MHz (7 cores), 3,000 MHz (8 cores), 3,000 MHz (9 cores), 3,000 MHz (10 cores), 3,000 MHz (11 cores), 3,000 MHz (12 cores), 2,550 MHz (13 cores), 2,550 MHz (14 cores), 2,550 MHz (15 cores), 2,550 MHz (16 cores), 2,550 MHz (17 cores), 2,550 MHz (18 cores), 2,550 MHz (19 cores), 2,550 MHz (20 cores), 2,550 MHz (21 cores), 2,550 MHz (22 cores), 2,550 MHz (23 cores), 2,550 MHz (24 cores), 2,550 MHz (25 cores), 2,550 MHz (26 cores), 2,550 MHz (27 cores), 2,550 MHz (28 cores), 2,550 MHz (29 cores), 2,550 MHz (30 cores), 2,550 MHz (31 cores), 2,550 MHz (32 cores)
Clock multiplier	20
Microarchitecture
ISA	x86-64 (x86)
Microarchitecture	Zen
Core Name	Naples
Core Family	23
Core Model	1
Core Stepping	B2
Process	14 nm
Transistors	19,200,000,000
Technology	CMOS
Die	213 mm²
MCP	Yes (4 dies)
Word Size	64 bit
Cores	32
Threads	64
Max Memory	2 TiB
Multiprocessing
Max SMP	1-Way (Uniprocessor)
Electrical
TDP	180 W
Tcase	0 °C – 81 °C
Packaging
Package	SP3, FCLGA-4094 (FC-OLGA)
Dimension	75.4 mm × 58.5 mm × 6.26 mm
Pitch	0.87 mm × 1 mm
Contacts	4094
Socket	SP3, LGA-4094

EPYC 7551P is a 64-bit 32-core x86 enterprise server microprocessor introduced by AMD in mid-2017. This processor is based on the Zen microarchitecture and is manufactured on a 14 nm process. The 7551P has a base frequency of 2 GHz with a turbo frequency of 3 GHz for up to 12 active cores. This chip has a TDP of 180 W and supports up to 2 TiB of octa-channel DDR4-2666 ECC memory.

Preliminary Data! Information presented in this article deal with a microprocessor or chip that was recently announced or leaked, thus missing information regarding its features and exact specification. Information may be incomplete and can change by final release.

Cache

Main article: Zen § Cache

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

L1$ 3 MiB 3,072 KiB 3,145,728 B L1I$ 2 MiB 2,048 KiB 2,097,152 B 32x64 KiB 4-way set associative   L1D$ 1 MiB 1,024 KiB 1,048,576 B 32x32 KiB 8-way set associative write-back L2$ 16 MiB 16,384 KiB 16,777,216 B 0.0156 GiB     32x512 KiB 8-way set associative write-back L3$ 64 MiB 65,536 KiB 67,108,864 B 0.0625 GiB     8x8 MiB 16-way set associative write-back

Memory controller

[Edit/Modify Memory Info]

	Integrated Memory Controller
	Max Type DDR4-2666 Supports ECC Yes Max Mem 2 TiB Controllers 8 Channels 8 Max Bandwidth 158.95 GiB/s 162,764.8 MiB/s 170.671 GB/s 170,671.263 MB/s 0.155 TiB/s 0.171 TB/s Bandwidth Single 19.89 GiB/s Double 39.72 GiB/s Quad 79.47 GiB/s Hexa 119.21 GiB/s Octa 158.95 GiB/s

Expansions

The EPYC 7551P has 128 Gen 3 PCIe lanes.

[Edit/Modify Expansions Info]

	Expansion Options
	PCIe Revision 3.0 Max Lanes 128 Configs 8x16, 32x4

Features

[Edit/Modify Supported Features]

Supported x86 Extensions & Processor Features

MMX MMX Extension EMMX Extended MMX Extension SSE Streaming SIMD Extensions SSE2 Streaming SIMD Extensions 2 SSE3 Streaming SIMD Extensions 3 SSSE3 Supplemental SSE3 SSE4.1 Streaming SIMD Extensions 4.1 SSE4.2 Streaming SIMD Extensions 4.2 SSE4a Streaming SIMD Extensions 4a AVX Advanced Vector Extensions AVX2 Advanced Vector Extensions 2 ABM Advanced Bit Manipulation BMI1 Bit Manipulation Instruction Set 1 BMI2 Bit Manipulation Instruction Set 2 FMA3 3-Operand Fused-Multiply-Add AES AES Encryption Instructions RdRand Hardware RNG SHA SHA Extensions ADX Multi-Precision Add-Carry CLMUL Carry-less Multiplication Extension F16C 16-bit Floating Point Conversion x86-16 16-bit x86 x86-32 32-bit x86 x86-64 64-bit x86 Real Real Mode Protected Protected Mode SMM System Management Mode FPU Integrated x87 FPU NX No-eXecute SMT Simultaneous Multithreading AMD-Vi AMD-Vi (I/O MMU virtualization) AMD-V AMD Virtualization SME Secure Memory Encryption TSME Transparent SME SEV Secure Encrypted Virtualization SenseMI SenseMI Technology