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< pezy‎ | pezy-scx

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General Info
Model NumberPEZY-SC4
Introduction2016 (announced)
2020 (launched)
General Specs
Frequency1,600 MHz
Process5 nm
Die740 mm²
Power dissipation640 W
Vcore0.55 V

PEZY-SC4 (PEZY Super Computer 4) is a fifth generation many-core microprocessor developed by PEZY set to be introduced in the early-2020s. This chip, which is planned to operate at 1.6 GHz, will incorporate 16,384 cores and dissipate 640 W. The PEZY-SC4 will power the ZettaScaler-4.x series of supercomputers.

DIL16 Blank.svg Preliminary Data! Information presented in this article deal with a microprocessor or chip that was recently announced or leaked, thus missing information regarding its features and exact specification. Information may be incomplete and can change by final release.


The SC4 will be introduced by PEZY along with their fourth-generation ZettaScaler-4.0 supercomputer series. The SC4 is set to incorporate 16,384 cores along with 8-way SMT support for a total of 131,072 threads, twice as many cores as its predecessor.

Operating at 1.6 GHz, the PEZY-SC4 will have a peak performance of 105 TFLOPS (single-precision) and 52.5 TFLOPS (double-precision) while consuming around 640 Watts. The PEZY-SC4 is expected to be manufactured on TSMC's 5 nm process.


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Memory controller[edit]

For main memory, the PEZY-SC4 supports 4 channels of 64-bit DDR5-4000 memory with ECC support for a total aggregated bandwidth of 107.3 GiB/s

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR5-4000
Supports ECCYes
Width64 bit
Max Bandwidth119.2 GiB/s
Single 29.8 GiB/s
Double 59.6 GiB/s
Quad 119.2 GiB/s

In addition to main memory bandwidth, the PEZY-SC4 supports Wide-IO with a width of 4,096 bit, twice of the SC3. As with the SC3, the SC4 will use ThruChip Interface (TCI) interfaces in order to communicate with the TCI-DRAM chips. This chip incorporates 8 interfaces, operating at 3 GHz for a bandwidth of 2.8 TiB/s per interface for a total aggregated bandwidth of 22.35 TB/s - twice the bandwidth of its predecessor.

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
MemoryWide I/O
Rate3,000 MHz
Width4,096 bit
Max Bandwidth22.35 TiB/s


With the SC4, PEZY plans to expand on the custom optics interface that was designed for the PEZY-SC3 for up to 512 lanes.

Facts about "PEZY-SC4 - PEZY"
base frequency1,600 MHz (1.6 GHz, 1,600,000 kHz) +
core count16,384 +
core voltage0.55 V (5.5 dV, 55 cV, 550 mV) +
designerPEZY +
die area740 mm² (1.147 in², 7.4 cm², 740,000,000 µm²) +
familyPEZY-SCx +
first announced2016 +
first launched2020 +
full page namepezy/pezy-scx/pezy-sc4 +
has ecc memory supporttrue + and false +
instance ofmicroprocessor +
ldate3000 +
manufacturerTSMC +
market segmentSupercomputer +
model numberPEZY-SC4 +
namePEZY-SC4 +
peak flops (double-precision)52,428,800,000,000 FLOPS (52,428,800,000 KFLOPS, 52,428,800 MFLOPS, 52,428.8 GFLOPS, 52.429 TFLOPS, 0.0524 PFLOPS, 5.24288e-5 EFLOPS, 5.24288e-8 ZFLOPS) +
peak flops (half-precision)209,715,200,000,000 FLOPS (209,715,200,000 KFLOPS, 209,715,200 MFLOPS, 209,715.2 GFLOPS, 209.715 TFLOPS, 0.21 PFLOPS, 2.097152e-4 EFLOPS, 2.097152e-7 ZFLOPS) +
peak flops (single-precision)104,857,600,000,000 FLOPS (104,857,600,000 KFLOPS, 104,857,600 MFLOPS, 104,857.6 GFLOPS, 104.858 TFLOPS, 0.105 PFLOPS, 1.048576e-4 EFLOPS, 1.048576e-7 ZFLOPS) +
power dissipation640 W (640,000 mW, 0.858 hp, 0.64 kW) +
process5 nm (0.005 μm, 5.0e-6 mm) +
supported memory typeDDR5-4000 +
technologyCMOS +
thread count131,072 +