Edit Values
P2020
General Info
Designer	Freescale
Manufacturer	IBM
Model Number	P2020
Market	Networking, Embedded
Introduction	June 16, 2008 (announced) 2009 (launched)
End-of-life	2023 (last order)
General Specs
Family	QorIQ
Series	P2
Frequency	800 MHz, 1,200 MHz, 1,333 MHz
Microarchitecture
ISA	Power ISA v2.03 (Power)
Microarchitecture	e500
Core Name	e500 v2
Process	45 nm
Technology	CMOS
Word Size	32 bit
Cores	2
Threads	2
Electrical
Power dissipation	8 W
Tjunction	0 °C – 125 °C
Packaging
Package TE-PBGA-II-689 (TE PBGA-II) Temperature-Enhanced Plastic BGA Dimension 31 mm x 31 mm Contacts 689

QorIQ P2020 is a 32-bit embedded dual-core POWER microprocessor introduced by Freescale in 2008. This networking/embedded processor, which is based on the e500 microarchitecture and is fabricated on a 45 nm SOI process, operates at 1.2 GHz and supports 64-bit DDR3-800 memory.

Cache

Main article: e500 § Cache

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

L1$ 128 KiB 131,072 B 0.125 MiB L1I$ 64 KiB 65,536 B 0.0625 MiB 2x32 KiB 8-way set associative   L1D$ 64 KiB 65,536 B 0.0625 MiB 2x32 KiB 8-way set associative   L2$ 512 KiB 0.5 MiB 524,288 B 4.882812e-4 GiB     1x512 KiB 8-way set associative Write-through

Memory controller

[Edit/Modify Memory Info]

	Integrated Memory Controller
	Max Type DDR3-800 Supports ECC Yes Controllers 1 Channels 1 Width 64 bit Max Bandwidth 5.96 GiB/s 6,103.04 MiB/s 6.4 GB/s 6,399.501 MB/s 0.00582 TiB/s 0.0064 TB/s Bandwidth Single 5.96 GiB/s

Expansions

• 3x 10/100/1000 Eithernet with SGMII
• 3x PCIe 1.0a controllers with 2 SerDes
• 1x USB 2.0
• SD/MMC
• SPI
• 2x I2C
• UART
• SEC 3.1 Security Acceleration

Block Diagram

Documents

• QorIQ P2 Series Product Brief
• P2 Platform Series