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Hi1620 - HiSilicon
< hisilicon‎ | hi16xx

Edit Values
General Info
ARM Holdings
Model NumberHi1620
IntroductionSeptember, 2018 (announced)
September, 2018 (launched)
General Specs
Frequency3,000 MHz
Core NameAres
Word Size64 bit
Max CPUs2 (Multiprocessor)
Max Memory512 GiB

Hi1620 is a planned octatetraconta-core 64-bit ARM server microprocessor set to be introduced by HiSilicon in late-2018. Fabricated by TSMC on a ? nm process, this chip incorporates 48 Ares cores operating at 3 GHz. The Hi1620 supports up to 512 GiB of quad-channel DDR4-2400 memory.

DIL16 Blank.svg Preliminary Data! Information presented in this article deal with a microprocessor or chip that was recently announced or leaked, thus missing information regarding its features and exact specification. Information may be incomplete and can change by final release.


Main article: Cortex-A76 § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$3.75 MiB
3,840 KiB
3,932,160 B
0.00366 GiB
L1I$2.25 MiB
2,304 KiB
2,359,296 B
0.0022 GiB
48x48 KiB8-way set associative 
L1D$1.5 MiB
1,536 KiB
1,572,864 B
0.00146 GiB
48x32 KiB8-way set associative 

L2$12 MiB
12,288 KiB
12,582,912 B
0.0117 GiB
  48x256 KiB8-way set associative 

L3$48 MiB
49,152 KiB
50,331,648 B
0.0469 GiB
  48x1 MiB16-way set associative 

Memory controller[edit]

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR4-2400
Supports ECCYes
Max Mem512 GiB
Width64 bit
Max Bandwidth71.53 GiB/s
Single 17.88 GiB/s
Double 35.76 GiB/s
Quad 71.53 GiB/s


[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIeRevision: 3.0
Max Lanes: 16
Configuration: 2x8


[Edit/Modify Supported Features]

Supported ARM Extensions & Processor Features
NEONAdvanced SIMD extension
CRC32CRC-32 checksum Extension

Utilizing devices[edit]

  • HiSilicon D06

This list is incomplete; you can help by expanding it.

Facts about "Hi1620 - HiSilicon"
Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
Hi1620 - HiSilicon#pcie +
base frequency3,000 MHz (3 GHz, 3,000,000 kHz) +
core count48 +
core nameAres +
designerHiSilicon + and ARM Holdings +
familyHi16xx +
first announcedSeptember 2018 +
first launchedSeptember 2018 +
full page namehisilicon/hi16xx/hi1620 +
has ecc memory supporttrue +
instance ofmicroprocessor +
isaARMv8 +
isa familyARM +
l1$ size3.75 MiB (3,840 KiB, 3,932,160 B, 0.00366 GiB) +
l1d$ description8-way set associative +
l1d$ size1.5 MiB (1,536 KiB, 1,572,864 B, 0.00146 GiB) +
l1i$ description8-way set associative +
l1i$ size2.25 MiB (2,304 KiB, 2,359,296 B, 0.0022 GiB) +
l2$ description8-way set associative +
l2$ size12 MiB (12,288 KiB, 12,582,912 B, 0.0117 GiB) +
l3$ description16-way set associative +
l3$ size48 MiB (49,152 KiB, 50,331,648 B, 0.0469 GiB) +
ldate3000 +
manufacturerTSMC +
market segmentServer +
max cpu count2 +
max memory524,288 MiB (536,870,912 KiB, 549,755,813,888 B, 512 GiB, 0.5 TiB) +
max memory channels4 +
microarchitectureAres +
model numberHi1620 +
nameHi1620 +
supported memory typeDDR4-2400 +
technologyCMOS +
thread count48 +
used byHiSilicon D06 +
word size64 bit (8 octets, 16 nibbles) +