|Introduction||September 5, 2000 (launched)|
|Bus speed||100 MHz|
|Bus rate||100 MT/s|
|Core Stepping||4, 5, 6, 7|
|Word Size||32 bit|
|Max Memory||4 GiB|
|Max SMP||1-Way (Uniprocessor)|
|Power dissipation||14.2 W|
|Vcore||2.0 V ± 0.1 V|
|VI/O||3.3675 V ± 7%|
|Tcase||0 °C – 85 °C|
K6-2+/533ACZ was a 32-bit x86 mobile microprocessor designed by AMD and introduced in late 2000. Based on the K6-III microarchitecture manufactured on a 0.18 µm process, this model operated at 533 MHz with a TDP of 18.0 W.
- Main article: K6-III § Cache
[Edit/Modify Cache Info]
is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU
by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.
The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.
Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.
Note: All units are in kibibytes
|1x32 KiB||2-way set associative|| |
|1x32 KiB||2-way set associative||write-back|
| || ||1x128 KiB||4-way set associative|| |
This processor has no integrated graphics processing unit.
- Auto-power down state
- Stop clock state
- "Mobile AMD-K6®-2+ Processor Data Sheet", AMD Publ. #23446, Rev. B, June 1, 2000