• 32-bit architecture
  ...]s. These architectures typically have a matching [[register file]] with [[registers]] width of 32 bits. === [[x86]] ===
  1 KB (137 words) - 19:55, 5 December 2019
• 64-bit architecture
  ...]s. These architectures typically have a matching [[register file]] with [[registers]] width of 64 bits. === [[x86]] ===
  2 KB (240 words) - 02:48, 17 March 2019
• intel/mcs-8/isa
  | registers = 7 ...an {{arch|8}} data and address bus. This architecture included seven 8-bit registers, 48 instructions, and interrupt capability.
  13 KB (2,079 words) - 09:11, 29 September 2019
• intel/microarchitectures/bonnell
  |isa=x86-64 ...as|Austin]] - [[wikipedia:Mount Bonnell|Mount Bonnell]], was Intel's first x86-compatible [[microarchitecture]] designed to target the ultra-low power mar
  38 KB (5,468 words) - 20:29, 23 May 2019
• intel/microarchitectures/goldmont
  |isa=x86-64 ...s and many ALU operations have 3 op/cycle throughput for 16, 32 and 64-bit registers. (8-bit ALU ops throughput is 2, 1.5 or 1 op per cycle).
  7 KB (956 words) - 23:05, 23 March 2020
• intel/microarchitectures/haswell (client)
  |isa=x86-64 * New memory model for {{x86|TSX|Transactional Synchronization Extensions}}
  27 KB (3,750 words) - 06:57, 18 November 2023
• intel/microarchitectures/sandy bridge (client)
  |isa=x86-64 ! Cores !! {{intel|Hyper-Threading|HT}} !! {{x86|AVX}} !! {{x86|AES}} !! [[IGP]] !! {{intel|Turbo Boost|TBT}} !! [[ECC]]
  84 KB (13,075 words) - 00:54, 29 December 2020
• intel/microarchitectures/skylake (client)
  |isa=x86-64 ! Cores !! {{intel|Hyper-Threading|HT}} !! {{x86|AVX}} !! {{x86|AVX2}} !! {{intel|Turbo Boost|TBT}} !! [[ECC]]
  79 KB (11,922 words) - 06:46, 11 November 2022
• intel/microarchitectures/ice lake (client)
  |isa=x86-64 Ice Lake introduced a number of {{x86|extensions|new instructions}}.
  23 KB (3,613 words) - 12:31, 20 June 2021
• x86/umip
  {{x86 title|UMIP}}{{x86 isa main}} '''User-Mode Instruction Prevention''' (UMIP) is an x86 security feature introduced in the Intel {{intel|Cannon Lake}}, {{intel|Gol
  2 KB (338 words) - 01:25, 30 December 2019
• amd/microarchitectures/k6
  |isa=x86-32 *** Short decode: Two x86 instructions that generate up to two micro-ops each
  4 KB (578 words) - 18:57, 22 May 2019
• amd/microarchitectures/zen
  |isa=x86-64 ! Cores !! Unlocked !! {{x86|AVX2}} !! [[SMT]] !! {{amd|XFR}} !! [[IGP]] !! [[ECC]] !! [[Multiprocessin
  79 KB (12,095 words) - 15:27, 9 June 2023
• amd/microarchitectures/zen 2
  |isa=x86-64 ! Cores !! Unlocked !! {{x86|AVX2}} !! [[SMT]] !! [[IGP]] !! [[ECC]] !! [[Multiprocessing|MP]]
  57 KB (8,701 words) - 22:11, 9 October 2022
• x86
  {{x86 isa main}} ...re is widely used in the [[desktop]] and [[server]] markets. Today, custom x86-based implementations are designed by a number of [[semiconductor companies
  3 KB (334 words) - 11:29, 10 July 2021
• intel/xeon e5
  | isa = x86-64 '''Xeon E5''' is a family of mid-range enterprise-level [[x86]] microprocessors. These server processors offer high performance, multi-so
  11 KB (1,395 words) - 08:36, 4 November 2020
• x86/extensions
  {{x86 title|Extensions}}{{x86 isa main}} The [[x86]] [[instruction set architecture|ISA]] has gone through numerous iterations
  6 KB (764 words) - 08:53, 7 June 2020
• intel/microarchitectures/merced
  ** Early zero bubble predictor using Target Address Registers controlled by the compiler ...d that must determine variable length instruction boundaries and translate x86 instructions into internal micro-ops. In contrast, Merced fetches fixed len
  7 KB (978 words) - 21:16, 20 January 2021
• x86/avx-512
  {{x86 title|Advanced Vector Extensions 512 (AVX-512)}}{{x86 isa main}} ...ber of {{arch|512}} [[SIMD]] [[x86]] [[instruction set]] extensions. The {{x86|extensions}} were formally introduced by [[Intel]] in July [[2013]] with fi
  83 KB (13,667 words) - 15:45, 16 March 2023
• power
  === Registers === * [[x86]]
  1 KB (133 words) - 07:30, 21 July 2018
• x86/tme
  {{x86 title|Total Memory Encryption (TME)}}{{x86 isa main}} ...emory Encryption''' ('''TME''') is a planned [[x86]] [[instruction set]] {{x86|extension}} proposed by [[Intel]] for a full physical memory encryption for
  6 KB (970 words) - 02:40, 17 December 2017

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