Page title matches

• amd/x86 (isa)
  #REDIRECT [[x86]]
  17 bytes (2 words) - 01:14, 17 May 2017

Page text matches

• intel/xeon
  | isa = x86-64 ...n''' (pronounced ''"Zee-On"'') is an extended family of high-performance [[x86]] microprocessors developed by [[Intel]] for server environments and non-co
  13 KB (1,417 words) - 12:37, 22 December 2018
• amd/epyc/9174f
  |isa=x86-64 |isa family=x86
  4 KB (693 words) - 01:48, 2 April 2023
• amd/epyc/9224
  |isa=x86-64 |isa family=x86
  4 KB (666 words) - 01:48, 2 April 2023
• microprocessor family
  ...uch as {{intel|execute disable|XD}}, {{amd|no execute|NX}}, and various {{x86|SSE}} extensions in the case of [[Intel]].
  1 KB (193 words) - 03:07, 1 May 2017
• 32-bit architecture
  === [[x86]] === ...all microarchitectures]] [[designer::AMD]] [[instruction set architecture::x86-32]]
  1 KB (137 words) - 19:55, 5 December 2019
• 64-bit architecture
  === [[x86]] === ...all microarchitectures]] [[designer::AMD]] [[instruction set architecture::x86-64]]
  2 KB (240 words) - 02:48, 17 March 2019
• amd/athlon
  | isa = x86 ...:AMD Athlon Processor x86 Code Optimization Guide.pdf|AMD Athlon Processor x86 Code Optimization Guide]]; Publication No. 22007; Revision K; Date February
  10 KB (1,163 words) - 10:41, 26 February 2019
• amd/am9080
  ...e agreement was later expanded in [[1982]] which grew to incorporate the [[x86]] family of microprocessors and which later grew into legal dispute that la
  5 KB (683 words) - 23:46, 7 March 2018
• intel/microarchitectures/bonnell
  |isa=x86-64 ...as|Austin]] - [[wikipedia:Mount Bonnell|Mount Bonnell]], was Intel's first x86-compatible [[microarchitecture]] designed to target the ultra-low power mar
  38 KB (5,468 words) - 20:29, 23 May 2019
• intel/microarchitectures/skylake (client)
  |isa=x86-64 ! Cores !! {{intel|Hyper-Threading|HT}} !! {{x86|AVX}} !! {{x86|AVX2}} !! {{intel|Turbo Boost|TBT}} !! [[ECC]]
  79 KB (11,922 words) - 06:46, 11 November 2022
• intel/microarchitectures/kaby lake
  |isa=x86-64 ! Cores !! {{intel|Hyper-Threading|HT}} !! {{x86|AVX}} !! {{x86|AVX2}} !! {{intel|Turbo Boost|TBT}} !! [[ECC]]
  38 KB (5,431 words) - 10:41, 8 April 2024
• intel/microarchitectures/cannon lake
  |isa=x86-64 Cannon Lake introduced a number of {{x86|extensions|new instructions}}. See {{intel|palm cove#New instructions|Palm
  7 KB (887 words) - 12:53, 5 August 2019
• x86/umip
  {{x86 title|UMIP}}{{x86 isa main}} '''User-Mode Instruction Prevention''' (UMIP) is an x86 security feature introduced in the Intel {{intel|Cannon Lake}}, {{intel|Gol
  2 KB (338 words) - 01:25, 30 December 2019
• 1998
  * May 28: AMD introduces the {{amd|K6-2}} family implementing {{x86|3DNow}} [[SIMD]] extension
  556 bytes (75 words) - 10:20, 28 January 2018
• intel/80386
  | arch = x86 ...nges brought about by 386 became the standard for all future {{arch|32}} [[x86]] processors, dubbed [[IA-32|i386-architecture]].
  4 KB (400 words) - 08:43, 5 December 2022
• amd/am386
  ...ess for AMD, allowing them become a fully fledged independent developer of x86 [[microprocessor]]s, as opposed to just a second source manufacturer. In 1985 [[Intel]] introduced its 3rd generation [[x86]] microprocessors, the {{intel|80386}} family. AMD had a cross-licensing ag
  8 KB (1,077 words) - 14:50, 2 April 2020
• intel/core m
  | isa = x86-64 '''Core M''' is a family of [[Consumer Ultra-Low Voltage]] (CULV) [[x86]] microprocessors introduced by [[Intel]] in 2014. Core M microprocessors h
  7 KB (949 words) - 20:01, 8 August 2018
• intel/80486
  | arch = x86 ...ter IPC performance, and an integrated [[FPU]]. The 486 became the first [[x86]] chip family to exceed one million transistors.
  8 KB (953 words) - 08:27, 29 October 2022
• intel/microarchitectures/80486
  |isa=x86-32
  1 KB (131 words) - 19:34, 30 November 2017
• amd/am486
  '''Am486''' was a family of {{arch|32}} 4th-generation [[x86]] microprocessors introduced by [[AMD]] in [[1993]]. Am486 chips were compa
  13 KB (1,897 words) - 09:30, 21 July 2021

View (previous 20 | next 20) (20 | 50 | 100 | 250 | 500)