• intel/core i7
  {{comp table header|main|6:Main processor|2:Turbo <small>(per active cores)</small>|4:Features}} {{comp table header|main|6:Main processor|2:Turbo <small>(per active cores)</small>|3:GPU|4:Features}}
  43 KB (5,739 words) - 21:30, 22 April 2024
• microprocessor
  ...may also serve as [[graphical processing unit]]s (GPUs), [[digital signal processor|signal processing units]] (DSPs), [[neural processing unit]] (NPUs), [[micr * '''[[digital signal processor]]''' ('''DSP''') - a microprocessor that specializes in the numerical manip
  8 KB (1,149 words) - 00:41, 16 September 2019
• intel/microarchitectures/goldmont
  ** Some vector instructions are faster, but like on {{\\|Airmont}}, none have throughput > * {{x86|XSAVEC|<code>XSAVEC</code>}} - Save processor extended states with compaction to memory
  7 KB (956 words) - 23:05, 23 March 2020
• intel/microarchitectures/haswell (client)
  ...or NOPs, CLC, some vector MOVs and some zeroing instructions (SUB, XOR and vector analogs). * {{x86|AVX2|<code>AVX2</code>}} - Advanced Vector Extensions 2; an extension that extends most integer instructions to 256 bi
  27 KB (3,750 words) - 06:57, 18 November 2023
• intel/microarchitectures/sandy bridge (client)
  * {{x86|AVX|<code>AVX</code>}} - Advanced Vector Extensions ...improved performance while saving power. Intel introduced a number of new vector computation ([[SIMD]]) and security instructions which improved [[floating
  84 KB (13,075 words) - 00:54, 29 December 2020
• intel/microarchitectures/skylake (client)
  *** Incorporates an [[image signal processor]] (ISP) ...emory QoS for higher resolution displays and the integrated [[image signal processor]] (ISP)
  79 KB (11,922 words) - 06:46, 11 November 2022
• intel/microarchitectures/kaby lake
  ...y Lake G processors. And the introduction of the first low power quad core processor. ! colspan="5" | [[Integrated Graphics Processor]] !! colspan="9" | Standards
  38 KB (5,431 words) - 10:41, 8 April 2024
• intel/microarchitectures/ice lake (client)
  * {{x86|RDPID|<code>RDPID</code>}} - Read Processor ID ** {{x86|AVX512VL|<code>AVX512VL</code>}} - AVX-512 Vector Length
  23 KB (3,613 words) - 12:31, 20 June 2021
• x86/umip
  ...rupt handler code. CR0 contains flags which control operating modes of the processor. User-mode code was never able to load values into these registers. Reading
  2 KB (338 words) - 01:25, 30 December 2019
• intel/core i3
  {{comp table header|main|7:Main processor|3:GPU}} {{comp table header|main|7:Main processor|3:GPU|Features}}
  25 KB (3,397 words) - 03:12, 3 October 2022
• intel/core i5
  {{comp table header|main|6:Main processor|2:Turbo <small>(per active cores)</small>|3:GPU|4:Features}} {{comp table header|main|6:Main processor|2:Turbo <small>(per active cores)</small>|3:GPU|4:Features}}
  34 KB (4,663 words) - 20:38, 20 February 2023
• intrinsity/fastmath
  | arch = 32-bit vector/matrix math processor + RISC cpu '''FastMATH''' was a family of matrix and vector math processors with an on-die [[RISC]] [[CPU]]s introduced by [[Intrinsity
  4 KB (464 words) - 17:41, 3 July 2016
• intrinsity/fastmath/fastmath-1.5
  ...orporates a high-performance [[MIPS]] CPU along with a powerful matrix and vector math unit. == Matrix and Vector Unit ==
  3 KB (317 words) - 16:30, 13 December 2017
• intrinsity/fastmath/fastmath-2
  ...orporates a high-performance [[MIPS]] CPU along with a powerful matrix and vector math unit. == Matrix and Vector Unit ==
  3 KB (318 words) - 16:30, 13 December 2017
• intrinsity/fastmath/fastmath-lp
  ...r math unit. This mode was a low-power (LP) version of the normal FastMATH processor, operating at half the speed. == Matrix and Vector Unit ==
  3 KB (334 words) - 16:31, 13 December 2017
• intrinsity/fastmath/fastmath-3
  ...orporates a high-performance [[MIPS]] CPU along with a powerful matrix and vector math unit. == Matrix and Vector Unit ==
  3 KB (306 words) - 16:31, 13 December 2017
• intel/microarchitectures/coffee lake
  ...cture by introducing two additional [[physical cores]] into its mainstream processor die. Those two cores also come with up to 2 MiB of LLC slice per core (for ...[[2011]]. In [[2006]] Intel introduced the first mainstream [[quad-core]] processor, the [[Core 2 Extreme QX6700]] which was based on the {{intel|Kentsfield|l=
  30 KB (4,192 words) - 13:48, 10 December 2023
• amd/microarchitectures/zen
  ! colspan="11" | AMD Zen-based processor brands ...c logo.png|75px|link=amd/epyc]] || {{amd|EPYC}} || High-performance Server Processor || [[8 cores|8]]-[[32 cores|32]] || {{tchk|no}} || {{tchk|yes}} || {{tchk|y
  79 KB (12,095 words) - 15:27, 9 June 2023
• amd/microarchitectures/zen 2
  ! colspan="11" | AMD Zen-based processor brands ...c logo.png|75px|link=amd/epyc]] || {{amd|EPYC}} || High-performance Server Processor || [[8 cores|8]]-[[64 cores|64]] || {{tchk|no}} || {{tchk|yes}} || {{tchk|y
  57 KB (8,701 words) - 22:11, 9 October 2022
• mediatek/helio/mt6795
  * OpenVG 1.1 vector graphics accelerator * Integrated image signal processor supports 20 MP
  5 KB (669 words) - 14:35, 5 August 2020

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