• buffer gate
  {{title|Buffer Gate}}{{logic gate A '''buffer''', is a basic [[logic gate]] that passes its input, unchanged, to its output. Its behavior is the
  3 KB (454 words) - 16:15, 11 August 2018
• cmos/static
  '''Static [[CMOS]]''' is a [[logic gate|logic]] circuit design technique whereby the output is always strongly driven due ...th the pull-up and pull-down networks are ON, the result is a [[crowbarred level]]. This result is typically an unwanted condition
  1 KB (221 words) - 18:07, 26 November 2018
• digital design
  ...al design has grown to included small [[microcontrollers]], [[programmable logic device|PLDs]] and [[soft processors]].
  682 bytes (91 words) - 12:10, 21 July 2018
• intel/3000
  ...he series was made using used [[bipolar]] [[schottky transistor-transistor logic|Schottky transistors]]. | {{\|3207}} || Quad Bipolar-to-MDS Level Shifter and Driver
  3 KB (308 words) - 05:03, 18 February 2020
• pass-transistor logic
  ...t [[logic level]]s directly come from the input. This is as opposed to the logic that connects the output node directly to {{vdd}} or {{gnd}}. ...For this reason, [[restoring logic]] must be added to restore the [[logic level]]s.
  767 bytes (115 words) - 22:32, 25 November 2015
• ti/tms1000
  ...g [[pMOS logic|pMOS]] technology, TI later expended the family into [[nMOS logic|nMOS]] and [[CMOS]]. | [[/tms1000|TMS1000]] || 1KB || 64x4 || 23 || [[pMOS logic|pMOS]] ||
  6 KB (711 words) - 04:39, 26 April 2017
• amd/am29100
  | {{\|Am29114}} || 8-level real-time [[interrupt]] controller ...done externally (e.g. using the {{\|Am29112}} [[microsequencer]] or custom logic) to handle [[subroutines]], and memory access.
  3 KB (323 words) - 11:26, 15 August 2017
• intel/mcs-8/isa
  ...l operations involving register-register operations such as arithmetic and logic operations only require one byte and take the following form: ...col 2=1 |op={{bin|00 XXX 111}} |act=Unconditionally return, down one stack level}}
  13 KB (2,079 words) - 09:11, 29 September 2019
• intel/microarchitectures/bonnell
  * 533 MT/s dual mode ([[gunning transceiver logic|GTL]] & [[CMOS]]) [[front side bus|FSB]] *** No level 3 cache
  38 KB (5,468 words) - 20:29, 23 May 2019
• intel/microarchitectures/saltwell
  *** No level 3 cache ...still a dual-issue [[superscalar]] but with in-order execution. Reordering logic is was still omitted due to power and area restrictions.
  7 KB (872 words) - 19:42, 30 November 2017
• intel/microarchitectures/sandy bridge (client)
  | {{intel|Sandy Bridge E|l=core}} || SNB-E || Workstations & entry-level servers ...="2" | {{intel|Celeron}} || style="text-align: left;" rowspan="2" | Entry-level Budget || [[1 cores|1]] || {{tchk|yes}} || {{tchk|yes}} || {{tchk|no}} || {
  84 KB (13,075 words) - 00:54, 29 December 2020
• intel/microarchitectures/skylake (client)
  ...=core}} || SKL-DT || {{intel|Greenlow|l=platform}} || Workstations & entry-level servers ...] || rowspan="2" | {{intel|Celeron}} || style="text-align: left;" | Entry-level Budget || rowspan="2" | [[dual-core|dual]] || {{tchk|no}} || {{tchk|no}} ||
  79 KB (11,922 words) - 06:46, 11 November 2022
• intel/microarchitectures/kaby lake
  ...{intel|Greenlow|l=platform}} || Workstation || GT2 || Workstations & entry-level servers ...=intel/celeron]] || {{intel|Celeron}} || style="text-align: left;" | Entry-level Budget || [[dual-core|dual]] || {{tchk|no}} || {{tchk|no}} || {{tchk|no}} |
  38 KB (5,431 words) - 10:41, 8 April 2024
• intel/microarchitectures/ice lake (client)
  ...lt 3 I/O subsystem on-die, significantly simplifying support at the system level. Ice Lake has four Thunderbolt 3 ports. All four ports have the same capabi On the platform level, there is a new integrated power delivery (FIVR) on both the PCH and the CP
  23 KB (3,613 words) - 12:31, 20 June 2021
• 5 nm lithography process
  In terms of raw cell-level density, the 5-nanometer node features silicon densities between 130-230 mi ...e]] successor to the company's [[N7 node]], featuring 1.84x improvement in logic density.
  11 KB (1,662 words) - 02:58, 2 October 2022
• microarchitecture
  ...SA) - I.E. it is the physical hardware organization (on the [[transistor]] level) of an architecture (e.g. [[CPU]], [[GPU]], [[FPU]], [[DSP]], [[Coprocessor The [[instruction set architecture]] (ISA) can be seen as a high-level contract between the architect and the programmer. It sets out to define ho
  3 KB (431 words) - 22:51, 21 November 2017
• intel/microarchitectures/coffee lake
  ...=core}} || CFL-E || Mehlow || Workstation || GT2 || Workstations and entry-level servers ...(2015).png|50px|link=intel/celeron]] || {{intel|Celeron}} || 4xxx || Entry-level Budget || [[dual-core|Dual]] || {{tchk|no}} || {{tchk|no}} || {{tchk|no}} |
  30 KB (4,192 words) - 13:48, 10 December 2023
• amd/microarchitectures/zen
  | [[File:amd ryzen 3 logo.png|75px|link=Ryzen 3]] || {{amd|Ryzen 3}} || Entry level Performance || [[quad-core|Quad]] || {{tchk|yes}} || {{tchk|yes}} || {{tchk | desc 5 = '''Performance Level'''<br><table><tr><td style="width: 50px;">'''9'''</td><td>Extreme (Ryzen Th
  79 KB (12,095 words) - 15:27, 9 June 2023
• amd/microarchitectures/zen 2
  | [[File:amd ryzen 3 logo.png|75px|link=Ryzen 3]] || {{amd|Ryzen 3}} || Entry level Performance || [[quad-core|Quad]] || {{tchk|yes}} || {{tchk|yes}} || {{tch Once per cycle the next address logic determines if branch instructions have been identified in the current 64-by
  57 KB (8,701 words) - 22:11, 9 October 2022
• intel/microarchitectures/gen9.5
  | Windows || Linux || Windows || Linux || [[High Level Shading Language|HLSL]] || Windows || Linux || Windows || Linux | Stream Output Logic (SOL) || The Stream Output Logic is responsible for outputting incoming object vertices into Stream Out Buff
  29 KB (3,752 words) - 13:14, 19 April 2023

View (previous 20 | next 20) (20 | 50 | 100 | 250 | 500)