• intel/microarchitectures/kaby lake
  ...e}} || KBL-H || || High-performance Graphics || GT2/GT3 || Ultimate mobile performance, mobile workstations ...ore}} || KBL-S || || Performance-optimized lifestyle || GT2/GT3 || Desktop performance to value, AiOs, and minis
  38 KB (5,431 words) - 10:41, 8 April 2024
• ambric/am2000
  ...}} (A) and later {{\|Am2045B}} had over 300 cores with maximum theoretical performance of over one trillion operations per second. Due to the [[wikipedia:2008 fin * 2x '''Compute Units''' (CU)
  11 KB (1,421 words) - 14:45, 9 December 2018
• amd/microarchitectures/zen
  ...e of covering the entire computing spectrum from fanless notebooks to high-performance desktop computers. Zen was officially launched on March 2, [[2017]]. Zen wa For performance desktop and mobile computing, Zen is branded as {{amd|Athlon}}, {{amd|Ryzen
  79 KB (12,095 words) - 15:27, 9 June 2023
• amd/microarchitectures/zen 2
  For performance desktop and mobile computing, Zen is branded as {{amd|Athlon}}, {{amd|Ryzen ...amd ryzen 3 logo.png|75px|link=Ryzen 3]] || {{amd|Ryzen 3}} || Entry level Performance || [[quad-core|Quad]] || {{tchk|yes}} || {{tchk|yes}} || {{tchk|some}} ||
  57 KB (8,701 words) - 22:11, 9 October 2022
• intel/microarchitectures/gen9.5
  ...s support different Graphics Tiers (GT) which provides different levels of performance. Some models also support an additional [[eDRAM]] side cache. == Performance ==
  29 KB (3,752 words) - 13:14, 19 April 2023
• intel/microarchitectures/gen9
  ...s support different Graphics Tiers (GT) which provides different levels of performance. Some models also support an additional [[eDRAM]] side cache. == Performance ==
  33 KB (4,255 words) - 17:41, 1 November 2018
• ibm/microarchitectures/power9
  POWER9-based microprocessors are fabricated on [[GlobalFoundries]]'s High-Performance [[14 nm process|14 nm]] (14HP) [[FinFET]] [[Silicon-On-Insulator]] (SOI) pr * Higher single-thread performance
  14 KB (1,905 words) - 23:38, 22 May 2020
• acorn/microarchitectures/arm1
  ...decc|VAX 11/780}}, the prototypes ended up achieveing between 2x to 4x the performance of the [[DEC]] {{decc|VAX 11/780}}; this is roughly equivalent to 10 times * Goal 1.5x performance of the {{decc|VAX 11/780}}
  12 KB (1,886 words) - 12:56, 14 January 2021
• amd/microarchitectures/zen 3
  | {{amd|Trento|l=core}}<!--s/a Milan page--> || ?/? || High-performance computing Zen 3 is fabricated on [[TSMC]]'s [[7 nm process|7nm+ process]] for the Core Compute Die (CCD), the same process used in Zen 2 Refresh processors, as well as [[
  15 KB (1,978 words) - 22:13, 6 April 2023
• intel/xeon platinum
  ...troduced by [[Intel]] in 2017. The Xeon Platinum series offers the highest performance, highest scalability, and highest flexibility. ...n E7}} and the {{\\|Xeon E5}} families. Xeon Platinum provides the highest performance and flexibility out of all the Xeon families, thus placing it above the {{\
  11 KB (1,476 words) - 17:13, 30 December 2022
• acorn/microarchitectures/arm2
  ...lining]] technique in order to improve performance and efficiency. At peak performance the ARM2 can reach 10 [[million instructions per second]] with an average o ...ddress translation is necessary and prepare ahead. This is done to improve performance because it can make use of [[Page-Mode DRAM]], allowing for more efficient
  14 KB (2,093 words) - 04:42, 10 July 2018
• x86/avx-512
  ...ction of execution resources due to die size or complexity constraints, or performance optimizations where execution resources are dynamically disabled if power o ...de>{{link|#SQRT}}</code> and <code>{{link|#DIV}}</code> instructions which compute full precision results. Also <code>RSQRT</code> and <code>{{link|#RCP}}</co
  83 KB (13,667 words) - 15:45, 16 March 2023
• amd/microarchitectures/vega
  ! rowspan="2" | Name !! rowspan="2" | Compute Units !! rowspan="2" | Shaders!! colspan="2" | [[Vulkan]] !! colspan="3" | ! rowspan="2" | Name !! rowspan="2" | Compute Units !! rowspan="2" | Shaders!! colspan="2" | [[Vulkan]] !! colspan="3" |
  4 KB (510 words) - 12:42, 16 June 2020
• microsoft/scorpio engine
  ...he ''Scorpio Engine'' most important goal was achieving true [[4K]] gaming performance according to John Sell, a Distinguished Engineer at Microsoft who presented ...ev kit can deliver a reported 6.6 TFLOPS with its four additional CUs. The performance of texture processing has also been increased to 187.5 G bilinear [[texels]
  15 KB (2,390 words) - 02:54, 17 May 2023
• neural processor
  ...ecute [[machine learning]] algorithms. NPUs are designed to accelerate the performance of common machine learning tasks such as image classification, machine tran ...ng are designed to accelerate the curating of new models. This is a highly compute-intensive operation that involves inputting an existing dataset (typically
  5 KB (640 words) - 16:27, 26 September 2023
• supercomputers/aurora
  ...l [[2015]], Aurora was planned to be delivered in [[2018]] and have a peak performance of 180 [[petaFLOPS]]. The system was expected to be the world's most powerf | Compute Nodes || >50,000
  3 KB (390 words) - 10:49, 11 May 2019
• intel/loihi
  Announced in September 2017, Loihi is predominantly a research chip meaning performance characteristics are not guaranteed. This is Intel's 5th chip in the neuromo ...arch, Intel Labs, HPC Developer Conference 2017 ("Leading The Evolution of Compute: Neuromorphic and Quantum Computing").
  12 KB (1,817 words) - 01:28, 1 October 2021
• nervana/microarchitectures/spring crest
  * 3x-4x+ performance ...or a total of 98,304 [[FLOPs]] each cycle for a total of up to 119 TOPS of compute. The MPUs are fed by 60 MiB of distributed SRAM. Spring Crest uses [[bfloat
  11 KB (1,646 words) - 13:35, 26 April 2020
• intel/cores/kaby lake g
  '''Kaby Lake G''' ('''KBL-G''') is the name of the core for [[Intel]]'s high-performance line of mobile processors based on the {{intel|Kaby Lake|l=arch}} microarch ***** 24 Compute Units
  5 KB (728 words) - 18:07, 12 July 2018
• amd/ryzen embedded
  ...[SMT]] and a {{amd|Vega|l=arch}} integrated graphics processor with 6 or 7 compute units in {{amd|FP6|package FP6|l=package}}.
  11 KB (1,642 words) - 03:53, 2 January 2021

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