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- | clock = 400 MHz | clock min = 32 MHz4 KB (434 words) - 03:31, 15 February 2016
- | clock min = | clock max =43 KB (5,739 words) - 21:30, 22 April 2024
- | clock = <!-- clock speed, e.g. "740 kHz" IF RANGE, USE PARAM BELOW! --> | clock min = <!-- clock min speed, e.g. "200 MHz" -->2 KB (266 words) - 00:54, 19 May 2016
- | clock min = 1 MHz | clock max = 31 MHz9 KB (1,061 words) - 22:55, 18 June 2019
- | clock = <!-- clock speed, e.g. "740 kHz" IF RANGE, USE PARAM BELOW! --> | clock min = 400 kHz4 KB (400 words) - 19:05, 24 May 2016
- | clock = <!-- clock speed, e.g. "740 kHz" IF RANGE, USE PARAM BELOW! --> | clock min = <!-- clock min speed, e.g. "200 MHz" -->4 KB (462 words) - 19:14, 13 October 2019
- | clock = <!-- clock speed, e.g. "740 kHz" IF RANGE, USE PARAM BELOW! --> | clock min = <!-- clock min speed, e.g. "200 MHz" -->3 KB (301 words) - 19:23, 13 October 2019
- | clock min = 1 MHz | clock max = 20 MHz2 KB (179 words) - 00:03, 3 February 2016
- | clock = <!-- clock speed, e.g. "740 kHz" IF RANGE, USE PARAM BELOW! --> | clock min = 340 kHz2 KB (274 words) - 18:29, 5 February 2016
- | clock = <!-- clock speed, e.g. "740 kHz" IF RANGE, USE PARAM BELOW! --> | clock min = 4.098 kHz6 KB (685 words) - 22:49, 5 February 2016
- | clock min = | clock max =4 KB (521 words) - 14:38, 11 June 2017
- | clock = <!-- clock speed, e.g. "740 kHz" IF RANGE, USE PARAM BELOW! --> | clock min = <!-- clock min speed, e.g. "200 MHz" -->2 KB (182 words) - 06:47, 22 January 2016
- | clock min = 6 MHz | clock max = 8 MHz2 KB (215 words) - 14:55, 4 February 2016
- | clock min = 1 MHz | clock max = 6 MHz2 KB (230 words) - 07:46, 28 February 2017
- | clock = 750 kHz | clock min = <!-- clock min speed, e.g. "200 MHz" -->2 KB (276 words) - 18:29, 29 January 2016
- | clock = <!-- clock speed, e.g. "740 kHz" IF RANGE, USE PARAM BELOW! --> | clock min = 100 kHz2 KB (280 words) - 00:57, 19 May 2016
- ...lementary topology|complementary topology]]. This type of logic allow high speed and low transistor count. However because of this very design, the output w ...side effect of this is that dynamic gates that are connected to the same [[clock signal]] cannot be directly cascaded since the monotonically falling output7 KB (1,159 words) - 21:01, 8 February 2019
- | bus speed = | clock multiplier = 244 KB (404 words) - 16:22, 13 December 2017
- | bus speed = | clock multiplier = 263 KB (401 words) - 14:24, 12 February 2019
- | bus speed = | clock multiplier = 283 KB (399 words) - 16:22, 13 December 2017