• intel/mcs-4/4004
  The 4004 has 16 pins that are used for i/o, memory controller, clock phases, power and reset. | 6 || Clock Phase 1 || rowspan="2" | Clock inputs || rowspan="2" |
  5 KB (748 words) - 21:37, 21 November 2021
• microprocessor
  ...serve as [[graphical processing unit]]s (GPUs), [[digital signal processor|signal processing units]] (DSPs), [[neural processing unit]] (NPUs), [[microcontro * '''[[digital signal processor]]''' ('''DSP''') - a microprocessor that specializes in the numer
  8 KB (1,149 words) - 00:41, 16 September 2019
• Timer
  ...alarm - POSIX|alarm]] which would generate the [[SIGALRM]] [[POSIX signals|signal]] after a specified number of seconds. Likewise, on [[Windows]], the SetTim * [[Real-time clock]]
  1 KB (179 words) - 11:43, 10 April 2014
• ideal logic gate
  ...ignal takes some time to settle down at the correct output while the ideal signal always does so instantly.]]
  1 KB (158 words) - 22:40, 20 December 2015
• cmos
  ...ffect of this is that dynamic gates that are connected to the same [[clock signal]] cannot be directly cascaded since the monotonically falling output is not
  7 KB (1,159 words) - 21:01, 8 February 2019
• amd/athlon
  | clock min = 500 MHz | clock max = 1400 MHz
  10 KB (1,163 words) - 10:41, 26 February 2019
• intel/microarchitectures/sandy bridge (client)
  **** Read: 32 B/cycle (@ ring [[clock]]) **** Write: 32 B/cycle (@ ring clock)
  84 KB (13,075 words) - 00:54, 29 December 2020
• intel/microarchitectures/skylake (client)
  *** Incorporates an [[image signal processor]] (ISP) ** DMI/PEG are now on a discrete clock domain with BCLK sitting on its own domain with full-range granularity (1 M
  79 KB (11,922 words) - 06:46, 11 November 2022
• intel/microarchitectures/kaby lake
  **** Read: 32 B/cycle (@ ring [[clock]]) **** Write: 32 B/cycle (@ ring clock)
  38 KB (5,431 words) - 10:41, 8 April 2024
• ambric/am2000
  | clock min = 1 MHz | clock max = 350 Mhz
  11 KB (1,421 words) - 14:45, 9 December 2018
• intel/microarchitectures/coffee lake
  ...ntroduced a refresh of Coffee Lake, adding more cores and increasing their clock frequencies. **** Read: 32 B/cycle (@ ring [[clock]])
  30 KB (4,192 words) - 13:48, 10 December 2023
• amd/microarchitectures/zen 2
  Bypassing the clock-gated fetch and decode units, and providing up to twice as many instruction ...to conserve die space and reduce signal path lengths which permits higher clock frequencies. The number of execution resources available reflects the densi
  57 KB (8,701 words) - 22:11, 9 October 2022
• qualcomm/msm6xxx/msm6000
  | clock multiplier = == Digital Signal Processing ==
  4 KB (424 words) - 03:32, 23 December 2021
• qualcomm/msm6xxx/msm6025
  | clock multiplier = == Digital Signal Processing ==
  4 KB (417 words) - 16:31, 13 December 2017
• qualcomm/msm6xxx/msm6050
  | clock multiplier = == Digital Signal Processing ==
  4 KB (419 words) - 16:31, 13 December 2017
• qualcomm/msm6xxx/msm6100
  | clock multiplier = == Digital Signal Processing ==
  4 KB (460 words) - 16:31, 13 December 2017
• qualcomm/msm6xxx/msm6550
  | clock multiplier = == Digital Signal Processing ==
  5 KB (485 words) - 09:54, 8 April 2023
• qualcomm/msm6xxx/msm6150
  | clock multiplier = == Digital Signal Processing ==
  4 KB (456 words) - 16:31, 13 December 2017
• qualcomm/msm6xxx/msm6200
  | clock multiplier = == Digital Signal Processing ==
  4 KB (388 words) - 16:31, 13 December 2017
• qualcomm/msm6xxx/msm6225
  | clock multiplier = == Digital Signal Processing ==
  4 KB (440 words) - 16:31, 13 December 2017

View (previous 20 | next 20) (20 | 50 | 100 | 250 | 500)