• intel/microarchitectures/bonnell
  ...nell]], was Intel's first x86-compatible [[microarchitecture]] designed to target the ultra-low power market. ! Platform !! Chipset !! Core !! Target
  38 KB (5,468 words) - 20:29, 23 May 2019
• intel/microarchitectures/saltwell
  ! Platform !! Core !! Target * Double the size of the branch prediction history table
  7 KB (872 words) - 19:42, 30 November 2017
• intel/microarchitectures/silvermont
  ! Platform !! Core !! Target ...al-issue design; however it has a pipeline that is 2 stages shorter with a branch misprediction penalty of 3 cycles lower. Silvermont is the first microarchi
  9 KB (1,160 words) - 09:35, 25 September 2019
• intel/microarchitectures/haswell (client)
  ! Core !! Abbrev !! Target * Reorder Buffer (ROB) was increased to 192 entries (up from 168)
  27 KB (3,750 words) - 06:57, 18 November 2023
• intel/microarchitectures/sandy bridge (client)
  ! Core !! Abbrev !! Target [[File:sandy bridge buffer window.png|right|350px]]
  84 KB (13,075 words) - 00:54, 29 December 2020
• intel/microarchitectures/skylake (client)
  ! Core !! Abbrev !! Platform !! Target ** Larger Line Fill Buffer?
  79 KB (11,922 words) - 06:46, 11 November 2022
• amd/microarchitectures/zen
  ! Core !! C/T !! Target ** Branch Predictor
  79 KB (12,095 words) - 15:27, 9 June 2023
• amd/microarchitectures/zen 2
  ! Core !! C/T !! Target *** Improved [[branch prediction unit]]
  57 KB (8,701 words) - 22:11, 9 October 2022
• qualcomm/microarchitectures/falkor
  ! Compiler !! Arch-Specific || Arch-Favorable || Arch-Target **** 3 instructions + 1 direct branch per cycle
  6 KB (822 words) - 13:01, 19 May 2021
• intel/microarchitectures/merced
  ** ROT: Instruction rotation, decoupling buffer * Branch Predictor
  7 KB (978 words) - 21:16, 20 January 2021
• intel/microarchitectures/skylake (server)
  ! Core !! Abbrev !! Platform !! Target [[File:skylake sp buffer windows.png|right|400px]]
  52 KB (7,651 words) - 00:59, 6 July 2022
• intel/microarchitectures/goldmont plus
  ! Core !! Abbrev !! Target *** Enhanced branch prediction
  9 KB (1,128 words) - 13:28, 17 July 2023
• cve/cve-2017-5753
  ...iant 1) vulnerability by making the microprocessor take the wrong [[branch target]]. ...code segment is identified, the attacker can then train the processor's [[branch predictor]] that the bounds check will likely be true. This is done by repe
  12 KB (1,869 words) - 10:01, 27 February 2019
• samsung/microarchitectures/m1
  ** Advanced [[branch predictor]] There are two pipeline stages for the branch predictor for generating addresses. There are three cycles for [[instructio
  13 KB (1,962 words) - 14:48, 21 February 2019
• samsung/microarchitectures/m3
  *** Larger branch prediction *** Larger [[ReOrder buffer]] (228 entries, from 100 entries)
  20 KB (3,149 words) - 10:44, 15 February 2020
• amd/microarchitectures/zen 4
  ...subset of the IOD facilities and additional peripherals tailored for their target market, a CCX, and a GPU. A CCX contains 8 CPU cores (fewer may be usable o ...calar, out-of-order, 2-way [[SMT]] microarchitecture with advanced dynamic branch prediction, 4-way decoding of [[x86]] instructions with a stack optimizer,
  13 KB (1,821 words) - 19:28, 13 November 2023
• nvidia/microarchitectures/denver
  ...cro-ops per-cycle directly from L1i cache. Denver has 7 execution units: 1 branch, 2 integer (1 has hardware multiply module), 2 FP/NEON (128-bit), 2 Load/St ...ction Predictor - gshare-agree). It also has Return Stack Buffer, Indirect Target Predictor and static predictor.
  6 KB (825 words) - 09:10, 11 February 2020
• arm holdings/microarchitectures/cortex-a76
  ** [[Branch-prediction]] ...essor with an 8-issue back end. The pipeline is 13 stages with an 11-cycle branch misprediction penalty. It has a 64 KiB [[level 1]] [[instruction cache]] an
  14 KB (2,183 words) - 17:15, 17 October 2020
• arm holdings/microarchitectures/cortex-a77
  ** [[Branch-prediction]] *** lower latency recovery from branch mispredict flushes
  17 KB (2,555 words) - 06:08, 16 June 2023
• arm holdings/microarchitectures/cortex-a78
  ** [[Branch-prediction]] *** Buffer size shrunk
  21 KB (3,067 words) - 09:25, 31 March 2022

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