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  • ...later also manufactured by Fairchild. Many early high-speed systems and [[supercomputers]] made use of those chips. ...ply switching to 100K series [[ECL]] chips from [[Schottky TTL]]; this was all done without making any architectural changes and maintaining 100% software
    4 KB (521 words) - 14:38, 11 June 2017
  • ...his team. While originally implemented [[Intel]]'s [[ia-64|Itanium ISA]], all later generations were based on the [[SPARC]] ISA. Most recently [[Phytium] ...The FT-64 processors were the workhorse behind the early Galaxy series of supercomputers. The chip was designed to work in modules of 8 processors (collectively cal
    2 KB (324 words) - 22:02, 26 June 2018
  • * '''Note:''' While a model has an unlocked multiplier, not all chipsets support overclocking. (see [[#Sockets/Platform|§Sockets]]) **** 12 cycles latency (All others)
    79 KB (12,095 words) - 15:27, 9 June 2023
  • ...of [[TOP500]] & [[Green500]] supercomputers as the world's most efficient supercomputers. ...x), and [[Suiren]] (328,480 cores, 48.90 kW, 271.782 TFlop/s Linpack Rmax) supercomputers (ranked 1, 2, and 3 respectively).
    4 KB (612 words) - 11:14, 22 September 2018
  • ...s dissipating 180 W. The PEZY-SC2 powers the [[ZettaScaler]]-2.x series of supercomputers. ...ecessor}}. The PEZY-SC2 powers many of the top [[Green500]] most efficient supercomputers with upward of 14 GFLOPS/watt in performance.
    5 KB (683 words) - 11:15, 22 September 2018
  • ...ned by [[PEZY]]. Those processors power many of [[Japan]]'s most efficient supercomputers. ...vides immersion cooling systems. Together, they have developed a series of supercomputers called [[ZettaScaler]].
    6 KB (838 words) - 09:33, 9 May 2019
  • '''ZettaScaler''' is a series of [[Japanese]] supercomputers using [[processors]] designed by [[PEZY]] and liquid cooling systems design ZettaScaler supercomputers are constructed using dense server aggregates called 'Bricks'. The system i
    7 KB (857 words) - 20:39, 13 January 2018
  • ...6]] [[many-core microprocessors]] designed by [[Intel]] since [[2012]] for supercomputers and workstations primarily aimed at scientists and researchers. Those proce ...e delays with their 10 nm process has caused them to push the architecture all the way back to 2018. In late 2017 Intel finally announce that they had can
    4 KB (444 words) - 01:38, 19 December 2017
  • |predecessor link=supercomputers/summit |successor link=supercomputers/olcf-6
    2 KB (236 words) - 20:40, 21 July 2019
  • ...tor processors. In an attempt to broaden their market, NEC extended beyond supercomputers to the conventional server and workstation market. This is done through the ...of up to 410 GB/s for load and store each. The SPU is designed to provide all basic functionalities a typical [[CPU]]. Because the SX-Aurora is not a typ
    16 KB (2,497 words) - 13:30, 15 May 2020
  • |predecessor link=supercomputers/hector |successor link=supercomputers/archer 2
    3 KB (330 words) - 14:51, 21 October 2019
  • |predecessor link=supercomputers/archer * 1.1 PiB all-flash Lustre BurstBuffer file system
    1 KB (200 words) - 01:15, 21 October 2019
  • ...the successor to the {{\\|SX|SX line of supercomputers}}. VEs depart from all prior generations by departing from the traditional self-hosted vector proc
    5 KB (648 words) - 09:21, 1 December 2019