• intel/microarchitectures/bonnell
  === Generation successor === ! First Generation !! !! Second Generation !! !! Third Generation
  38 KB (5,468 words) - 20:29, 23 May 2019
• intel/microarchitectures/haswell (client)
  For desktop and mobile, Haswell is branded as 4th Generation Intel {{intel|Core}} processors. For server class processors, Intel branded ...expands on them considerably in the execution engine with wider execution units and additional scheduler ports.
  27 KB (3,750 words) - 06:57, 18 November 2023
• intel/microarchitectures/sandy bridge (client)
  ...i5}}, {{intel|Core i7}} processors. For workstations it's branded as first generation {{intel|Xeon E3}}. **** Execution Units
  84 KB (13,075 words) - 00:54, 29 December 2020
• intel/microarchitectures/skylake (client)
  For desktop and mobile, Skylake is branded as 6th Generation Intel {{intel|Core i3}}, {{intel|Core i5}}, {{intel|Core i7}} processors. F ...FP-add unit on port 1 removed in favour of running all FP math on the FMA units.
  79 KB (11,922 words) - 06:46, 11 November 2022
• amd/microarchitectures/zen
  ...op APUs (2020)</td></tr><tr><td style="width: 50px;">'''5'''</td><td>Third generation Zen (Zen 3)(2020)</td></tr></table> ** Traditional design for cores without shared blocks (e.g. shared SIMD units)
  79 KB (12,095 words) - 15:27, 9 June 2023
• amd/microarchitectures/zen 2
  ...s a new fetch block address. If no branches are expected it calculates the address of the next sequential block. Branches are evaluated much later in the inte ...s, is flushed otherwise. It includes an optimization for calls to the next address, an IA-32 idiom to obtain a copy of the instruction pointer enabling positi
  57 KB (8,701 words) - 22:11, 9 October 2022
• pezy/pezy-scx/pezy-sc2
  '''PEZY-SC2''' ('''PEZY Super Computer 2''') is a third generation [[many-core microprocessor]] developed by [[PEZY]] and introduced in early Introduced by [[PEZY]] along with their second-generation [[ZettaScaler]]-2.0 supercomputer series, the SC2 incorporates 2,048 cores
  5 KB (683 words) - 11:15, 22 September 2018
• intel/microarchitectures/gen9.5
  '''Gen9.5''' (''Generation 9.5'') is the [[microarchitecture]] for [[Intel]]'s [[graphics processing u | GT1 || Contains 1 slice with 12 execution units.
  29 KB (3,752 words) - 13:14, 19 April 2023
• intel/microarchitectures/gen9
  '''Gen9''' (''Generation 9'') is the [[microarchitecture]] for [[Intel]]'s [[graphics processing uni | GT1 || Contains 1 slice with 12 execution units.
  33 KB (4,255 words) - 17:41, 1 November 2018
• intel/microarchitectures/merced
  ** Early zero bubble predictor using Target Address Registers controlled by the compiler ** 64-entry Target Address Cache
  7 KB (978 words) - 21:16, 20 January 2021
• ibm/microarchitectures/z14
  | Two radiator pumps or two Water Conditioning Units (WCUs) in the case of water cooling. ...ccessor to {{\\|z13}}, offering a large set of enhancements over the prior generation in all key areas such as scalability, security, and performance.
  8 KB (1,204 words) - 14:02, 23 September 2019
• intel/microarchitectures/skylake (server)
  ...-Threading|HT}} !! {{intel|Turbo Boost|TBT}} !! {{x86|AVX-512}} !! AVX-512 Units !! {{intel|Ultra Path Interconnect|UPI}} links !! Scalability ...logies not found in the client configuration. In addition to the execution units that were added, the cache hierarchy has changed for the server core as wel
  52 KB (7,651 words) - 00:59, 6 July 2022
• microsoft/scorpio engine
  ...previous generational chip. The entire memory subsystem was redesigned to address the major deficiencies in prior chips. In previous chip, Microsoft chose to ...ow the CPU accesses the memory has not been detailed. As with the previous generation, a bidirectional bus sits between the [[memory controllers]] and the CPUs a
  15 KB (2,390 words) - 02:54, 17 May 2023
• pezy/pezy-scx
  ...[[data cache]]. Complex instructions are processed by the Special Function Units (SFU) located in each city. A fair amount of sacrifices were made in order ...'''City''' is made of 64 KiB of [[L2 cache]], a number of special function units, and 4 smaller blocks called "Villages". A '''village''' consists of four p
  6 KB (838 words) - 09:33, 9 May 2019
• intel/microarchitectures/cascade lake
  ...-Threading|HT}} !! {{intel|Turbo Boost|TBT}} !! {{x86|AVX-512}} !! AVX-512 Units !! {{intel|Ultra Path Interconnect|UPI}} links !! Scalability ** Execution units
  32 KB (4,535 words) - 05:44, 9 October 2022
• samsung/microarchitectures/m3
  The M3 was fabricated on Samsung's second generation [[10 nm process|10LPP (Low Power Plus) process]]. **** new fuse address generation and memory µOP support
  20 KB (3,149 words) - 10:44, 15 February 2020
• movidius/microarchitectures/shave v2.0
  ** Parallel functional units controlled by VLIW instructions ...architecture. There are independent SHAVE cores, with up to eight in this generation may be chained together. Cores benefit from zero penalty from their two nei
  12 KB (1,749 words) - 19:05, 20 January 2021
• cavium/microarchitectures/vulcan
  *** Execution Units **** Wider FP Units (128-bit, up from 64-bit)
  17 KB (2,449 words) - 22:11, 4 October 2019
• amd/microarchitectures/zen 4
  ...teger/address and two floating point instruction schedulers, 3-way address generation, 5-way integer execution. 4-way 256-bit wide floating point execution, a sp * Five-level paging; Max. physical and linear address size raised from 48 to 52 and 57 bits respectively
  13 KB (1,821 words) - 19:28, 13 November 2023
• arm holdings/microarchitectures/cortex-a76
  ...eady to be fetched. Additionally, there is a return stack which stores the address and instruction set state ({{arm|AArch32}}/R14 or {{arm|AArch64}}/X30) on b ===== Execution Units =====
  14 KB (2,183 words) - 17:15, 17 October 2020

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