• cray/interconnects/slingshot
  * Improved QoS
  3 KB (384 words) - 05:45, 8 September 2020
• intel/microarchitectures/skylake (client)
  ** Improved underlying implementation of the memory QoS for higher resolution displays and the integrated [[image signal processor] ...e of full range shift by default, the operating system can set the minimum QoS, maximum frequency and power/performance hints when desired. The final resu
  79 KB (11,922 words) - 06:46, 11 November 2022
• amd/microarchitectures/zen 2
  *** QoS Monitoring and Enforcement ...a package as on Intel CPUs, so each CCX corresponds to one QoS domain. L2 QoS monitoring and enforcement is not supported.
  57 KB (8,701 words) - 22:11, 9 October 2022
• cavium/microarchitectures/cnmips
  * QoS accelerator ...C</th><th>Encryption</th><th>Compression</th><th>RegEx</th><th>TCP</th><th>QoS</th></tr>
  7 KB (870 words) - 19:38, 23 June 2017
• cavium/octeon
  ...C</th><th>Encryption</th><th>Compression</th><th>RegEx</th><th>TCP</th><th>QoS</th></tr> ...ardware accelerators for packet I/O processing, [[encryption]], [[TCP]], [[QoS]], compression/decompression, and [[RegEx]]. Additionally, these models sup
  11 KB (1,489 words) - 09:25, 30 December 2020
• cavium/octeon/cn3005-300bg350-scp
  ...rdware security communication accelerators including units for encryption, QoS, and TCP acceleration. This MPU supports up to 2 GiB of DDR2-533 memory. |qos=Yes
  4 KB (438 words) - 16:10, 13 December 2017
• cavium/octeon/cn3005-400bg350-scp
  ...rdware security communication accelerators including units for encryption, QoS, and TCP acceleration. This MPU supports up to 2 GiB of DDR2-533 memory. |qos=Yes
  4 KB (438 words) - 16:10, 13 December 2017
• cavium/octeon/cn3005-500bg350-scp
  ...rdware security communication accelerators including units for encryption, QoS, and TCP acceleration. This MPU supports up to 2 GiB of DDR2-533 memory. |qos=Yes
  4 KB (438 words) - 16:10, 13 December 2017
• cavium/octeon/cn3005-300bg350-cp
  ...n accelerators including units for high-performance packet I/O processing, QoS, and TCP acceleration. This MPU supports up to 2 GiB of DDR2-533 memory. |qos=Yes
  4 KB (422 words) - 16:10, 13 December 2017
• cavium/octeon/cn3005-400bg350-cp
  ...n accelerators including units for high-performance packet I/O processing, QoS, and TCP acceleration. This MPU supports up to 2 GiB of DDR2-533 memory. |qos=Yes
  4 KB (422 words) - 16:10, 13 December 2017
• cavium/octeon/cn3005-500bg350-cp
  ...n accelerators including units for high-performance packet I/O processing, QoS, and TCP acceleration. This MPU supports up to 2 GiB of DDR2-533 memory. |qos=Yes
  4 KB (422 words) - 16:10, 13 December 2017
• cavium/octeon/cn3010-300bg525-scp
  ...rdware security communication accelerators including units for encryption, QoS, and TCP acceleration. This MPU supports up to 2 GiB of DDR2-533 ECC memory |qos=Yes
  4 KB (465 words) - 16:10, 13 December 2017
• cavium/octeon/cn3010-400bg525-scp
  ...rdware security communication accelerators including units for encryption, QoS, and TCP acceleration. This MPU supports up to 2 GiB of DDR2-533 ECC memory |qos=Yes
  4 KB (465 words) - 16:10, 13 December 2017
• cavium/octeon/cn3010-500bg525-scp
  ...rdware security communication accelerators including units for encryption, QoS, and TCP acceleration. This MPU supports up to 2 GiB of DDR2-533 ECC memory |qos=Yes
  4 KB (465 words) - 16:10, 13 December 2017
• cavium/octeon/cn3010-300bg525-cp
  ...n accelerators including units for high-performance packet I/O processing, QoS, and TCP acceleration. This MPU supports up to 2 GiB of DDR2-533 ECC memory |qos=Yes
  4 KB (449 words) - 16:10, 13 December 2017
• cavium/octeon/cn3010-400bg525-cp
  ...n accelerators including units for high-performance packet I/O processing, QoS, and TCP acceleration. This MPU supports up to 2 GiB of DDR2-533 ECC memory |qos=Yes
  4 KB (449 words) - 16:10, 13 December 2017
• cavium/octeon/cn3010-500bg525-cp
  ...n accelerators including units for high-performance packet I/O processing, QoS, and TCP acceleration. This MPU supports up to 2 GiB of DDR2-533 ECC memory |qos=Yes
  4 KB (449 words) - 16:10, 13 December 2017
• cavium/octeon/cn3110-300bg868-nsp
  ...ption]], [[compression]] & decompression, [[RegEx]] engine, [[TCP]], and [[QoS]]. This MPU supports up to 4 GiB of 64-bit DDR2-667 ECC memory. |qos=Yes
  4 KB (474 words) - 16:10, 13 December 2017
• cavium/octeon/cn3110-400bg868-nsp
  ...ption]], [[compression]] & decompression, [[RegEx]] engine, [[TCP]], and [[QoS]]. This MPU supports up to 4 GiB of 64-bit DDR2-667 ECC memory. |qos=Yes
  4 KB (471 words) - 16:10, 13 December 2017
• cavium/octeon/cn3110-500bg868-nsp
  ...ption]], [[compression]] & decompression, [[RegEx]] engine, [[TCP]], and [[QoS]]. This MPU supports up to 4 GiB of 64-bit DDR2-667 ECC memory. |qos=Yes
  4 KB (471 words) - 16:11, 13 December 2017

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