• intel/microarchitectures/bonnell
  * Instruction Queue of 32 entries (16 entries/thread) ** L1 Instruction Cache
  38 KB (5,468 words) - 20:29, 23 May 2019
• intel/microarchitectures/saltwell
  * Larger instruction fetch *** 32 [[KiB]] 8-way [[set associative]] instruction
  7 KB (872 words) - 19:42, 30 November 2017
• intel/microarchitectures/silvermont
  * {{x86|MOVBE|<code>MOVBE</code>}} - Move Big-Endian instruction *** 32 [[KiB]] 8-way [[set associative]] instruction, 64 B line size
  9 KB (1,160 words) - 09:35, 25 September 2019
• intel/microarchitectures/haswell (client)
  * {{x86|MOVBE|<code>MOVBE</code>}} - Move Big-Endian instruction Haswell TLB consists of dedicated level one TLB for instruction cache and another one for data cache. Additionally there is a unified secon
  27 KB (3,750 words) - 06:57, 18 November 2023
• intel/microarchitectures/sandy bridge (client)
  *** Instruction Queue Sandy Bridge [[TLB]] consists of dedicated L1 TLB for instruction cache (ITLB) and another one for data cache (DTLB). Additionally there is a
  84 KB (13,075 words) - 00:54, 29 December 2020
• intel/microarchitectures/skylake (client)
  **** instruction window is now 64 Bytes (from 32) Skylake TLB consists of dedicated L1 TLB for instruction cache (ITLB) and another one for data cache (DTLB). Additionally there is a
  79 KB (11,922 words) - 06:46, 11 November 2022
• amd/microarchitectures/k6
  ** Fetch ** Operand Fetch
  4 KB (578 words) - 18:57, 22 May 2019
• amd/microarchitectures/zen
  *** BP is now decoupled from fetch stage ** Larger instruction scheduler
  79 KB (12,095 words) - 15:27, 9 June 2023
• amd/microarchitectures/zen 2
  Zen 2 inherits most of the design from {{\\|Zen+}} but improves the instruction stream bandwidth and floating-point throughput performance. *** 0.5x L1 instruction cache (32 KiB, down from 64 KiB)
  57 KB (8,701 words) - 22:11, 9 October 2022
• intel/microarchitectures/gen9.5
  | Vertex Fetch (VF) || The Vertex Fetch stage, in response to 3D Primitive Processing commands, is responsible for ...porting architecture specific registers (ARF). The EU can co-issue to four instruction processing units, including two FPUs, a branch unit, and a message send uni
  29 KB (3,752 words) - 13:14, 19 April 2023
• intel/microarchitectures/gen9
  | Vertex Fetch (VF) || The Vertex Fetch stage, in response to 3D Primitive Processing commands, is responsible for ...porting architecture specific registers (ARF). The EU can co-issue to four instruction processing units, including two FPUs, a branch unit, and a message send uni
  33 KB (4,255 words) - 17:41, 1 November 2018
• ibm/microarchitectures/power9
  *** 5 stages eliminated from fetch to compute vs {{\\|POWER8}} ** Instruction grouping at dispatch has been removed
  14 KB (1,905 words) - 23:38, 22 May 2020
• acorn/microarchitectures/arm1
  ...order to advance the development of their own [[RISC]] processor. The ARM instruction set design started in 1983. A reference model was written in [[BBC BASIC]] ==== Fetch ====
  12 KB (1,886 words) - 12:56, 14 January 2021
• intel/microarchitectures/merced
  ** IPG: Get next instruction pointer ** FET: Fetch from instruction cache
  7 KB (978 words) - 21:16, 20 January 2021
• if
  * [[Instruction Fetch]] (IF)
  168 bytes (21 words) - 17:17, 21 June 2017
• acorn/microarchitectures/arm2
  ==== Fetch ==== ...olds awaiting instructions until execution, it therefore holds a number of instruction sufficient to ensure instructions are always executing at all cycles on all
  14 KB (2,093 words) - 04:42, 10 July 2018
• ibm/microarchitectures/z14
  ** Improved instruction delivery * '''ICM''' - Instruction cache & merge
  8 KB (1,204 words) - 14:02, 23 September 2019
• x86/sme
  '''Secure Memory Encryption''' ('''SME''') is an [[x86]] [[instruction set]] {{x86|extension}} introduced by [[AMD]] for page-granular memory encr ...page. In other words, memory accesses such as guest [[page tables]] and [[instruction fetches]] are always private, regardless of the value of the C-bit (i.e., i
  7 KB (1,115 words) - 19:03, 7 May 2020
• samsung/microarchitectures/m1
  ** 4-way instruction decode Mongoose 1 TLB consists of dedicated L1 TLB for instruction cache (ITLB) and another one for data cache (DTLB). Additionally there is a
  13 KB (1,962 words) - 14:48, 21 February 2019
• samsung/microarchitectures/m3
  *** Larger [[instruction queue]] (40 entries, up from 24) *** Larger [[instruction fetch]] (48B/cycle, up from 24B/cycle)
  20 KB (3,149 words) - 10:44, 15 February 2020

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