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R-Car H2 - Renesas
Edit Values | |||||||||||
R-Car H2 | |||||||||||
General Info | |||||||||||
Designer | Renesas, ARM Holdings | ||||||||||
Manufacturer | TSMC | ||||||||||
Model Number | H2 | ||||||||||
Part Number | R8A7790 | ||||||||||
Market | Embedded | ||||||||||
Introduction | March 25, 2013 (announced) June, 2014 (launched) | ||||||||||
General Specs | |||||||||||
Family | R-Car | ||||||||||
Series | 2nd Gen | ||||||||||
Frequency | 1,500 MHz, 1,000 MHz, 780 MHz | ||||||||||
Microarchitecture | |||||||||||
ISA | ARMv7 (ARM), SuperH (SuperH) | ||||||||||
Microarchitecture | Cortex A15, Cortex A7, SH-4A | ||||||||||
Core Name | Cortex A15, Cortex A7, SH-4A | ||||||||||
Process | 28 nm | ||||||||||
Technology | CMOS | ||||||||||
Word Size | 32 bit | ||||||||||
Cores | 9 | ||||||||||
Threads | 9 | ||||||||||
Multiprocessing | |||||||||||
Max SMP | 1-Way (Uniprocessor) | ||||||||||
Electrical | |||||||||||
Vcore | 1.0 V | ||||||||||
VI/O | 3.3, 1.8 | ||||||||||
Packaging | |||||||||||
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R-Car H2 is a high-end embedded nona-core SoC for the automotive industry introduced by Renesas in early 2013. The H2 incorporates four Cortex-A15 cores operating at 1.5 GHz, four Cortex-A7 cores operating at 1 GHz, and one SH-4A core operating at 780 MHz for real-time processing. This SoC incorporates Imagination's PowerVR G6400 GPU operating at 550 MHz and supports up to dual-channel DDR3-1600 memory.
Contents
Cache[edit]
- Main articles: Cortex-A15 § Cache and Cortex-A7 § Cache
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller[edit]
Integrated Memory Controller
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Expansions[edit]
- Flash ROM and SRAM, Data bus width: 8 or 16 bits
- PCI Express2.0 (1 lane)
- USB 3.0 Host interface × 1 port (wPHY)
- USB 2.0 Host interface × 3 port (wPHY)
- SD Host interface × 4 ch (SDXC, UHS-I)
- Multimedia card interface × 2 ch
- Serial ATA interface × 2 ch
- I²C bus interface × 8 ch
- Serial communication interface (SCIF) × 10 ch
- Quad serial peripheral interface (QSPI) × 1 ch (for boot)
- Clock-synchronized serial interface (MSIOF) × 4 ch (SPI/IIS)
- Ethernet controller (IEEE802.3u, RMII, without PHY)
Graphics[edit]
Integrated Graphics Information
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Features[edit]
[Edit/Modify Supported Features]
Supported ARM Extensions & Processor Features
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Block Diagram[edit]
Dev Board ("LAGER")[edit]
- 210 mm x 180 mm
- R-Car H2
- 68 MiB serial flash memory
- 4 GiB DDR3-DRAM-1600; 1x 64-bit configuration
- RS-232C, UART, USB, SD, LAN, SATA, PCIe , CAN and MLB interfaces (partially via connector)
- HDMI and LVDS display-out
- switches, LEDs, I/O expansion header
Categories:
- all microprocessor models
- microprocessor models by renesas
- microprocessor models by renesas based on cortex a15
- microprocessor models by renesas based on cortex a7
- microprocessor models by renesas based on sh-4a
- microprocessor models by arm holdings
- microprocessor models by arm holdings based on cortex a15
- microprocessor models by arm holdings based on cortex a7
- microprocessor models by arm holdings based on sh-4a
- microprocessor models by tsmc
Facts about "R-Car H2 - Renesas"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | R-Car H2 - Renesas#package + |
base frequency | 1,500 MHz (1.5 GHz, 1,500,000 kHz) +, 1,000 MHz (1 GHz, 1,000,000 kHz) + and 780 MHz (0.78 GHz, 780,000 kHz) + |
core count | 9 + |
core name | Cortex A15 +, Cortex A7 + and SH-4A + |
core voltage | 1 V (10 dV, 100 cV, 1,000 mV) + |
designer | Renesas + and ARM Holdings + |
family | R-Car + |
first announced | March 25, 2013 + |
first launched | June 2014 + |
full page name | renesas/r-car/h2 + |
has ecc memory support | false + |
instance of | microprocessor + |
integrated gpu | PowerVR G6400 + |
integrated gpu base frequency | 550 MHz (0.55 GHz, 550,000 KHz) + |
integrated gpu designer | Imagination Technologies + |
integrated gpu execution units | 1 + |
io voltage | 3.3 V (33 dV, 330 cV, 3,300 mV) + and 1.8 V (18 dV, 180 cV, 1,800 mV) + |
isa | ARMv7 + and SuperH + |
isa family | ARM + and SuperH + |
l1$ size | 576 KiB (589,824 B, 0.563 MiB) + |
l1d$ size | 288 KiB (294,912 B, 0.281 MiB) + |
l1i$ size | 288 KiB (294,912 B, 0.281 MiB) + |
l2$ size | 2.5 MiB (2,560 KiB, 2,621,440 B, 0.00244 GiB) + |
ldate | June 2014 + |
main image | + |
manufacturer | TSMC + |
market segment | Embedded + |
max cpu count | 1 + |
max memory bandwidth | 11.92 GiB/s (12,206.08 MiB/s, 12.799 GB/s, 12,799.003 MB/s, 0.0116 TiB/s, 0.0128 TB/s) + |
max memory channels | 2 + |
microarchitecture | Cortex A15 +, Cortex A7 + and SH-4A + |
model number | H2 + |
name | R-Car H2 + |
package | FCBGA-831 + |
part number | R8A7790 + |
process | 28 nm (0.028 μm, 2.8e-5 mm) + |
series | 2nd Gen + |
smp max ways | 1 + |
supported memory type | DDR3-1600 + |
technology | CMOS + |
thread count | 9 + |
word size | 32 bit (4 octets, 8 nibbles) + |