Edit Values
AMD Athlon MP 2800+
General Info
Designer	AMD
Manufacturer	AMD
Model Number	Athlon MP 2800+
Part Number	AMSN2800DUT4C
Market	Server
Introduction	May 6, 2003 (announced) May 6, 2003 (launched)
Release Price	$275
Shop	Amazon
General Specs
Family	Athlon MP
Locked	Yes
Frequency	2,133 MHz
Bus type	FSB
Bus speed	133 MHz
Bus rate	266 MT/s
Clock multiplier	16
CPUID	6A0
Microarchitecture
Microarchitecture	K7
Platform	Athlon MP
Chipset	AMD-760MP
Core Name	Barton
Core Family	6
Core Model	10
Core Stepping	0, 1
Process	130 nm
Transistors	54,300,000
Technology	CMOS
Die	101 mm²
Word Size	32 bit
Cores	1
Threads	1
Max Memory	4 GiB
Multiprocessing
Max SMP	2-Way (Multiprocessor)
Electrical
Vcore	1.6 V
TDP	60 W
TDP (Typical)	47.2 W
Tjunction	0 °C – 90 °C
Tcase	0 °C – 90 °C
Tstorage	-40 °C – 100 °C
Packaging
Package OPGA-453 (PGA) Dimension 49.53 mm x 49.53 mm x 1.942 mm Pitch 1.27 mm Pins 453 Interconnect Socket A (PGA-462)

Athlon MP 2800+' (OPN AMSN2800DUT4C) based on the last-generation Barton core was a 32-bit x86 multiprocessor developed by AMD and introduced in early 2003 for the server and workstation market. This MPU, which operated at 2.13 GHz with a FSB transfer rate of 266 MT/s (x16 multiplier), was manufactured on a newer 130 nm process.

Cache

Main article: K7 § Cache

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

L1$ 128 KiB 131,072 B 0.125 MiB L1I$ 64 KiB 65,536 B 0.0625 MiB 1x64 KiB 2-way set associative   L1D$ 64 KiB 65,536 B 0.0625 MiB 1x64 KiB 2-way set associative   L2$ 512 KiB 0.5 MiB 524,288 B 4.882812e-4 GiB     1x512 KiB 16-way set associative

Graphics

This MPU has no integrated graphics processing unit.

Features

[Edit/Modify Supported Features]

	Supported x86 Extensions & Processor Features
	MMX MMX Extension EMMX Extended MMX Extension 3DNow! 3DNow! Extension E3DNow! Extended 3DNow! Extension SSE Streaming SIMD Extensions x86-16 16-bit x86 x86-32 32-bit x86 Real Real Mode Protected Protected Mode SMM System Management Mode FPU Integrated x87 FPU SmartMP SmartMP Technology

• Advanced Configuration and Power Interface
  • Halt State
  • Stop Grant State

Documents

Datasheets

• AMD Athlon MP Processor Model 10 Data Sheet for Multiprocessor Platforms; Publication # 26426 Rev. C; Issue Date: October 2003.

Others

• System Considerations for Dual AMD Athlon MP Processors in Tower and 1U Form Factors; Publication # 25325; Rev: B; August 2002.