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=== KaiXian ZX-A === | === KaiXian ZX-A === | ||
{{main|via_technologies/microarchitectures/isaiah|l1=VIA's Isaiah}} | {{main|via_technologies/microarchitectures/isaiah|l1=VIA's Isaiah}} | ||
− | KaiXian ZX-A were the first series of processors released by Zhaoxin. Those processors were based on the same architecture as [[VIA Technologies]] {{via|Isaiah|l=arch}} and | + | KaiXian ZX-A were the first series of processors released by Zhaoxin. Those processors were based on the same architecture as [[VIA Technologies]] {{via|Isaiah|l=arch}} and where manufactured on a [[40 nm process]]. For all practical purposes, those chips are identical to VIA's {{via|Nano}} parts. |
=== KaiXian ZX-B === | === KaiXian ZX-B === | ||
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Announced at Semicon China 2017, the KX-5000 (formerly ZX-D) introduces the largest set of the improvements. Those SoCs are based on {{zhaoxin|WuDaoKou|l=arch}}, fabricated on [[HLMC]]'s 28nm, and is considered the first truly zhaoxin-developed architecture. Among the many improvements such as higher integration (incorporating the [[GPU]] and [[memory controller]] on-die), those processors now support dual-channel DDR4 memory and support supports HD 4K decoding. | Announced at Semicon China 2017, the KX-5000 (formerly ZX-D) introduces the largest set of the improvements. Those SoCs are based on {{zhaoxin|WuDaoKou|l=arch}}, fabricated on [[HLMC]]'s 28nm, and is considered the first truly zhaoxin-developed architecture. Among the many improvements such as higher integration (incorporating the [[GPU]] and [[memory controller]] on-die), those processors now support dual-channel DDR4 memory and support supports HD 4K decoding. | ||
− | * '''ISA:''' Everything up to | + | * '''ISA:''' Everything up to AVX2 (SMM, FPU, NX, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AES, SHA, AVX, and AVX2) |
* '''Tech:''' {{intel|VT-x}}/{{intel|EPT}}, {{intel|TXT}} | * '''Tech:''' {{intel|VT-x}}/{{intel|EPT}}, {{intel|TXT}} | ||
− | * '''Mem:''' Up 64 GiB of dual-channel | + | * '''Mem:''' Up 64 GiB of dual-channel 2311 MT/s DDR4 |
<!-- NOTE: | <!-- NOTE: | ||
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{{main|zhaoxin/microarchitectures/lujiazui|l1=LuJiaZui microarchitecture}} | {{main|zhaoxin/microarchitectures/lujiazui|l1=LuJiaZui microarchitecture}} | ||
The KX-6000 (formerly ZX-E) is a planned series of processors based on {{zhaoxin|LuJiaZui|l=arch}} set to be fabricated on [[TSMC]]'s [[16 nm]]. | The KX-6000 (formerly ZX-E) is a planned series of processors based on {{zhaoxin|LuJiaZui|l=arch}} set to be fabricated on [[TSMC]]'s [[16 nm]]. | ||
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== See Also == | == See Also == | ||
* [[Loongson]] | * [[Loongson]] |
Facts about "KaiXian (ZX/KX) - Zhaoxin"
designer | Zhaoxin + and VIA Technologies + |
first announced | 2016 + |
first launched | 2016 + |
full page name | zhaoxin/kaixian + |
instance of | microprocessor family + |
instruction set architecture | x86 + |
main designer | Zhaoxin + |
manufacturer | TSMC + and HLMC + |
microarchitecture | Isaiah +, Zhangjiang +, WuDaoKou + and LuJiaZui + |
name | KaiXian + |
process | 40 nm (0.04 μm, 4.0e-5 mm) + and 28 nm (0.028 μm, 2.8e-5 mm) + |
technology | CMOS + |
word size | 64 bit (8 octets, 16 nibbles) + |