Editing zhaoxin/kaixian

{{zhaoxin title|KaiXian (ZX/KX)}}
{{ic family
| title             = KaiXian
| image             = 
| caption           = 
| no image          = Yes
| developer         = Zhaoxin
| developer 2       = VIA Technologies
| manufacturer      = TSMC
| manufacturer 2    = HLMC
| type              = Microprocessors
| first announced   = 2016
| first launched    = 2016
| isa               = x86
| microarch         = Isaiah
| microarch 2       = Zhangjiang
| microarch 3       = WuDaoKou
| microarch 4       = LuJiaZui
| word              = 64 bit
| proc              = 40 nm
| proc 2            = 28 nm
| tech              = CMOS
| clock min         = 
| clock max         = 
| package           = 
| package 2         = 
| package 3         = 
| socket            = 
| socket 2          = 

| succession       = Yes
| predecessor      = QuadCore
| predecessor link = via_technologies/quadcore
| successor        = 
| successor link   = 
}}
'''KaiXian''' ('''ZX'''/'''KX''') is a family of [[x86]] microprocessors developed by [[Zhaoxin]] for the [[Chinese]] market.

== Overview ==
KaiXian is a family of [[x86]] microprocessors designed by [[Zhaoxin]] as part of China's national security initiative which attempts to reduce the reliance on foreign technology (e.g., [[Intel]]) and to gain greater control over their intellectual property. Those processors are [[x86]]-compatible with Intel's processors and are capable of booting all modern operating systems such as Red Hat Enterprise Linux and Windows 10.

== Models ==
=== KaiXian ZX-A ===
{{main|via_technologies/microarchitectures/isaiah|l1=VIA's Isaiah}}
KaiXian ZX-A were the first series of processors released by Zhaoxin. Those processors were based on the same architecture as [[VIA Technologies]] {{via|Isaiah|l=arch}} and where manufactured on a [[40 nm process]]. For all practical purposes, those chips are identical to VIA's {{via|Nano}} parts.

=== KaiXian ZX-B ===
ZX-B series models were identical to ZX-A except that they are fabricated in mainland [[China]] on [[HLMC]]'s 40 nm process. 

=== KaiXian ZX-C ===
{{main|zhaoxin/microarchitectures/zhangjiang|l1=ZhangJiang microarchitecture}}
ZX-C which is based on the {{zhaoxin|ZhangJiang|l=arch}} microarchitecture introduced a number of enhancements including extending the architecture to support up to [[8 cores]]. With many respect they are very similar to VIA's {{via|QuadCore}}. Since those parts were manufactured on TSMC's [[28 nm process]], they have lower power consumption and thus higher clock speed.

=== KaiXian KX-5000 ===
{{main|zhaoxin/microarchitectures/wudaokou|l1=WuDaoKou microarchitecture}}
Announced at the end of 2017, the KX-5000 (formerly ZX-D) introduces the largest set of the improvements. Those SoCs are baased on {{zhaoxin|WuDaoKou|l=arch}}, fabricated on [[HLMC]]'s 28nm, and is considered the first truly zhaoxin-developed architecture. Among the many improvements such as higher integration (incorporating the [[GPU]] and [[memory controller]] on-die), those processors now support dual-channel DDR4 memory and support supports HD 4K decoding.

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{{comp table start}}
<table class="comptable sortable tc4">
{{comp table header|main|5:List of WuDaoKou-based KaiXian Processors}}
{{comp table header|cols|Family|Launched|Cores|L2|%Frequency}}
{{#ask: [[Category:microprocessor models by zhaoxin]] [[microarchitecture::WuDaoKou]] [[series::KX-5000]]
 |?full page name
 |?model number
 |?family
 |?first launched
 |?core count
 |?l2$ size
 |?base frequency#GHz
 |?max memory#GiB
 |?has ecc memory support
 |format=template
 |template=proc table 3
 |userparam=7
 |mainlabel=-
}}
{{comp table count|ask=[[Category:microprocessor models by zhaoxin]] [[microarchitecture::WuDaoKou]] [[series::KX-5000]]}}
</table>
{{comp table end}}

== See Also ==
* [[Loongson]]
designer	Zhaoxin + and VIA Technologies +
first announced	2016 +
first launched	2016 +
full page name	zhaoxin/kaixian +
instance of	microprocessor family +
instruction set architecture	x86 +
main designer	Zhaoxin +
manufacturer	TSMC + and HLMC +
microarchitecture	Isaiah +, Zhangjiang +, WuDaoKou + and LuJiaZui +
name	KaiXian +
process	40 nm (0.04 μm, 4.0e-5 mm) + and 28 nm (0.028 μm, 2.8e-5 mm) +
technology	CMOS +
word size	64 bit (8 octets, 16 nibbles) +