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|designer||Zhaoxin + and VIA Technologies +|
|first announced||2016 +|
|first launched||2016 +|
|full page name||zhaoxin/kaixian +|
|instance of||microprocessor family +|
|instruction set architecture||x86 +|
|main designer||Zhaoxin +|
|manufacturer||TSMC + and HLMC +|
|microarchitecture||Isaiah +, Zhangjiang +, WuDaoKou + and LuJiaZui +|
|process||40 nm (0.04 μm, 4.0e-5 mm) + and 28 nm (0.028 μm, 2.8e-5 mm) +|
|word size||64 bit (8 octets, 16 nibbles) +|