Editing umich/microarchitectures/vanilla-5

{{title|Vanilla-5 - Microarchitectures}}
{{microarchitecture
|atype=CPU
|name=Vanilla-5
|designer=University of Michigan
|designer 2=University of California
|designer 3=Cornell University
|designer 4=University of California
|manufacturer=TSMC
|process=16 nm
|type=Pipelined
|oooe=No
|speculative=No
|renaming=No
|stages=5
|decode=1
|isa=RISC-V
|extension=Integer
|extension 2=Multiply
|l1i=4 KiB
|l1i per=core
|l1d=4 KiB
|l1d per=core
}}
'''Vanilla-5''' is a custom [[RISC-V]] core microarchitecture designed specifically for the {{\\|Celerity}} SoC. The work is a joint effort by the Bespoke Silicon Group at the University of Washington, Cornell University, University of Michigan, and UC San Diego.

== Process technology ==
Vanilla-5 is integrated into the {{\\|Celerity}} SoC which is fabricated on [[TSMC]] [[16 nm process]].

== Overview ==
Vanilla-5 is a custom-designed [[RISC-V]] core designed by the {{\\|Celerity}} SoC team for that chip. The core is a fully synthesized design that implements the {{riscv|extensions|RV32IM}} ISA (base as well as the integer and multiply extensions). Vanilla-5 was designed to take up very little silicon area. For that reason it uses an incredibly simple design - it's an [[in-order]], [[single-issue]], [[pipelined|5-stage]] design. Each core incorporates a 32-entry, 32b register file which is implemented using two 1R1W latch-based [[sram|memory]] as well as a 4 KiB of private [[level 1]] [[instruction cache]] and a private 4 KiB of private level 1 [[data cache]].

The Vanilla-5 core is integrated into the {{\\|Celerity}} SoC where it's used as part of a [[manycore]] array of 496 tiles. Each tile comprises a Vanilla-5 core and a router. The core is silicon-proven capable of up to 1.4 GHz.

== Die ==
* [[TSMC]] [[16 nm process]]
* 24,251 µm² (0.024 mm²) die area


:[[File:vanilla-5 core.png|600px]]


:[[File:vanilla-5 (annotated).png|600px]]


'''Routing:'''

:[[File:vanilla-5 routing.png|600px]]

=== Breakdown ===
{| class="wikitable"
! Type !! Area (µm²) !! %
|-
| IMEM || 6691 || 27.59
|-
| DMEM || 6691 || 27.59
|-
| RF || 2008 || 8.28
|-
| Core logic || 2473 || 10.20
|-
| ALU || 485 || 2.00
|-
| Div || 412 || 1.70
|-
| Mult || 301 || 1.24
|-
| Pipeline/other || 1275 || 5.26
|-
| NoC || 1881 || 7.76
|-
| Endpoint FIFO || 303 || 1.25
|-
| Credit counter || 23 || 0.09
|-
| Router || 1555 || 6.41
|-
| Endcap/welltap || 281 || 1.16
|-
| Filler || 1635 || 6.74
|-
| Unutilized || 2591 || 10.68
|-
| Total || 24251 || 100.00
|}

== Source core ==
The Vanilla-5 core is open source and can be found on https://bitbucket.org/taylor-bsg/bsg_manycore/src/master/v/vanilla_bean/

== See also ==
* {{\\|Celerity}}

== Bibliography ==
* {{bib|vlsi|2019}}
* {{bib|hc|29}}
codename	Vanilla-5 +
designer	University of Michigan +, University of California + and Cornell University +
full page name	umich/microarchitectures/vanilla-5 +
instance of	microarchitecture +
instruction set architecture	RISC-V +
manufacturer	TSMC +
microarchitecture type	CPU +
name	Vanilla-5 +
pipeline stages	5 +
process	16 nm (0.016 μm, 1.6e-5 mm) +