From WikiChip
Information for "umich/microarchitectures/celerity"
Basic information
Display title | Celerity - Microarchitectures |
Default sort key | umich/microarchitectures/celerity |
Page length (in bytes) | 2,085 |
Page ID | 35760 |
Page content language | English (en) |
Page content model | wikitext |
Indexing by robots | Allowed |
Number of redirects to this page | 0 |
Counted as a content page | Yes |
Number of subpages of this page | 0 (0 redirects; 0 non-redirects) |
Page protection
Edit | Allow all users (infinite) |
Move | Allow all users (infinite) |
Edit history
Page creator | David (talk | contribs) |
Date of page creation | 22:05, 20 January 2020 |
Latest editor | David (talk | contribs) |
Date of latest edit | 01:14, 21 January 2020 |
Total number of edits | 4 |
Total number of distinct authors | 1 |
Recent number of edits (within past 90 days) | 0 |
Recent number of distinct authors | 0 |
Page properties
Transcluded templates (11) | Templates used on this page:
|
Facts about "Celerity - Microarchitectures"
codename | Celerity + |
designer | University of Michigan +, University of Washington +, Cornell University + and University of California + |
full page name | umich/microarchitectures/celerity + |
instance of | microarchitecture + |
instruction set architecture | RISC-V + |
manufacturer | TSMC + |
microarchitecture type | CPU + |
name | Celerity + |
process | 16 nm (0.016 μm, 1.6e-5 mm) + |