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Latest revision Your text
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|die width=8.61 mm
 
|die width=8.61 mm
 
|word size=64 bit
 
|word size=64 bit
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|core count=9
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|core count=10
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|thread count=9
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|thread count=10
 
|max cpus=1
 
|max cpus=1
 
|v core=0.8 V
 
|v core=0.8 V
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|package module 1={{packages/renesas/fcbga-1255}}
 
|package module 1={{packages/renesas/fcbga-1255}}
 
}}
 
}}
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'''R-Car H3''' is a {{arch|64}} [[nona-core]] [[ARM]] SoC designed by [[Renesas]] for the automotive industry and introduced in 2016. The H3 incorporates four {{armh|Cortex-A57}} cores, four {{armh|Cortex-A53}} cores, and a dual-core lock-step {{armh|Cortex-R7}} for real-time processing. This chip supports up to quad-channel LPDDR4-3200 memory. This chip incorporates the [[imagination technologies|Imagination]]'s {{imgtec|PowerVR GX6650}} [[GPU]].
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'''R-Car H3''' is a {{arch|64}} [[deca-core]] [[ARM]] SoC designed by [[Renesas]] for the automotive industry and introduced in 2016. The H3 incorporates four {{armh|Cortex-A57}} cores, four {{armh|Cortex-A53}} cores, and a two {{armh|Cortex-R7}} cores for real-time processing. This chip supports up to quad-channel LPDDR4-3200 memory. This chip incorporates the [[imagination technologies|Imagination]]'s {{imgtec|PowerVR GX6650}} [[GPU]].
  
 
This model is an [[SiP]] variant of the {{\\|H3}} which include the DDR memory on-package.
 
This model is an [[SiP]] variant of the {{\\|H3}} which include the DDR memory on-package.
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{{main|arm holdings/microarchitectures/cortex-a53#Memory_Hierarchy|arm holdings/microarchitectures/cortex-a57#Memory_Hierarchy|l1=Cortex-A53 § Cache|l2=Cortex-A57 § Cache}}
 
{{main|arm holdings/microarchitectures/cortex-a53#Memory_Hierarchy|arm holdings/microarchitectures/cortex-a57#Memory_Hierarchy|l1=Cortex-A53 § Cache|l2=Cortex-A57 § Cache}}
 
{{cache size
 
{{cache size
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|l1 cache=640 KiB
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|l1 cache=704 KiB
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|l1i cache=352 KiB
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|l1i cache=384 KiB
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|l1i break=4x48+5x32 KiB
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|l1i break=4x48+6x32 KiB
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|l1d cache=288 KiB
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|l1d cache=320 KiB
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|l1d break=9x32 KiB
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|l1d break=10x32 KiB
 
|l2 cache=2.5 MiB
 
|l2 cache=2.5 MiB
 
}}
 
}}
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== Block Diagram ==
 
== Block Diagram ==
 
:: [[File:r-car h3 block.png|750px]]
 
:: [[File:r-car h3 block.png|750px]]
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== Die Shot ==
 
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* [[16 nm process]], CMOS FinFET
 
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* 12.94 mm × 8.61 mm
 
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* 111.36 mm² die size
 
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:: [[File:r-car h3 die shot.png|650px]]
 
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== References ==
 
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* Takahashi, Chikafumi, et al. "4.5 A 16nm FinFET heterogeneous nona-core SoC complying with ISO26262 ASIL-B: Achieving 10− 7 random hardware failures per hour reliability." Solid-State Circuits Conference (ISSCC), 2016 IEEE International. IEEE, 2016.
 

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Facts about "R-Car H3 (SiP) - Renesas"
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"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
R-Car H3 (SiP) - Renesas#package +
core count9 +
core nameCortex-A53 +, Cortex-A57 + and Cortex-R7 +
core voltage0.8 V (8 dV, 80 cV, 800 mV) +
designerRenesas + and ARM Holdings +
die area111.36 mm² (0.173 in², 1.114 cm², 111,360,000 µm²) +
die length12.94 mm (1.294 cm, 0.509 in, 12,940 µm) +
die width8.61 mm (0.861 cm, 0.339 in, 8,610 µm) +
familyR-Car +
first announcedDecember 2, 2015 +
first launchedMarch 2018 +
full page namerenesas/r-car/h3 (sip) +
has ecc memory supportfalse +
instance ofmicroprocessor +
integrated gpuPowerVR GX6650 +
integrated gpu designerImagination Technologies +
io voltage3.3 V (33 dV, 330 cV, 3,300 mV) +
isaARMv8 +
isa familyARM +
l1$ size640 KiB (655,360 B, 0.625 MiB) +
l1d$ size288 KiB (294,912 B, 0.281 MiB) +
l1i$ size352 KiB (360,448 B, 0.344 MiB) +
l2$ size2.5 MiB (2,560 KiB, 2,621,440 B, 0.00244 GiB) +
ldateMarch 2018 +
main imageFile:r-car h3 (sip).png +
manufacturerTSMC +
market segmentEmbedded +
max cpu count1 +
max memory bandwidth47.68 GiB/s (48,824.32 MiB/s, 51.196 GB/s, 51,196.01 MB/s, 0.0466 TiB/s, 0.0512 TB/s) +
max memory channels4 +
microarchitectureCortex-A53 +, Cortex-A57 + and Cortex-R7 +
model numberH3 (SiP) +
nameR-Car H3 (SiP) +
packageFCBGA-1255 +
part numberR8J77950 +
process16 nm (0.016 μm, 1.6e-5 mm) +
series3rd Gen +
smp max ways1 +
supported memory typeLPDDR4-3200 +
technologyCMOS +
thread count9 +
word size64 bit (8 octets, 16 nibbles) +