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{{renesas title|R-Car H3 (SiP)}}
 
{{renesas title|R-Car H3 (SiP)}}
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{{chip
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{{mpu}}
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|name=R-Car H3 (SiP)
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'''R-Car H3''' is a {{arch|64}} [[nona-core]] [[ARM]] SoC designed by [[Renesas]] for the automotive industry and introduced in 2016. The H3 incorporates four {{armh|Cortex-A57}} cores, four {{armh|Cortex-A53}} cores, and a single {{armh|Cortex-R7}} core for real-time processing. This chip supports up to quad-channel LPDDR4-3200 memory.
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|image=r-car h3 (sip).png
 
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|designer=Renesas
 
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|designer 2=ARM Holdings
 
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|manufacturer=TSMC
 
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|model number=H3 (SiP)
 
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|part number=R8J77950
 
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|market=Embedded
 
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|first announced=December 2, 2015
 
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|first launched=March, 2018
 
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|family=R-Car
 
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|series=3rd Gen
 
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|isa=ARMv8
 
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|isa family=ARM
 
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|microarch=Cortex-A53
 
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|microarch 2=Cortex-A57
 
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|microarch 3=Cortex-R7
 
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|core name=Cortex-A53
 
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|core name 2=Cortex-A57
 
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|core name 3=Cortex-R7
 
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|process=16 nm
 
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|technology=CMOS
 
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|die area=111.36 mm²
 
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|die length=12.94 mm
 
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|die width=8.61 mm
 
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|word size=64 bit
 
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|core count=9
 
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|thread count=9
 
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|max cpus=1
 
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|v core=0.8 V
 
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|v io=3.3 V
 
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|package module 1={{packages/renesas/fcbga-1255}}
 
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}}
 
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'''R-Car H3''' is a {{arch|64}} [[nona-core]] [[ARM]] SoC designed by [[Renesas]] for the automotive industry and introduced in 2016. The H3 incorporates four {{armh|Cortex-A57}} cores, four {{armh|Cortex-A53}} cores, and a dual-core lock-step {{armh|Cortex-R7}} for real-time processing. This chip supports up to quad-channel LPDDR4-3200 memory. This chip incorporates the [[imagination technologies|Imagination]]'s {{imgtec|PowerVR GX6650}} [[GPU]].
 
  
 
This model is an [[SiP]] variant of the {{\\|H3}} which include the DDR memory on-package.
 
This model is an [[SiP]] variant of the {{\\|H3}} which include the DDR memory on-package.
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Samples for the H3 were available starting December 2015 with Renesas expecting mass production to begin in March 2018 and reach a volume of 100,000 units per month in March 2019.
 
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== Cache ==
 
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{{main|arm holdings/microarchitectures/cortex-a53#Memory_Hierarchy|arm holdings/microarchitectures/cortex-a57#Memory_Hierarchy|l1=Cortex-A53 § Cache|l2=Cortex-A57 § Cache}}
 
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{{cache size
 
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|l1 cache=640 KiB
 
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|l1i cache=352 KiB
 
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|l1i break=4x48+5x32 KiB
 
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|l1d cache=288 KiB
 
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|l1d break=9x32 KiB
 
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|l2 cache=2.5 MiB
 
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}}
 
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== Memory controller ==
 
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{{memory controller
 
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|type=LPDDR4-3200
 
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|ecc=No
 
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|controllers=1
 
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|channels=4
 
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|width=32 bit
 
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|max bandwidth=47.68 GiB/s
 
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|bandwidth schan=11.92 GiB/s
 
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|bandwidth dchan=23.84 GiB/s
 
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|bandwidth qchan=47.68 GiB/s
 
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}}
 
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== Expansions ==
 
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* PCI Express2.0 (1 lane) x 2 ch
 
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* USB 3.0 Host interface (DRD) × 1 ports (wPHY)
 
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* USB 2.0 Host/Function/OTG interface × 2 ports (wPHY)
 
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* SD Host interface × 4 ch (SDR104)
 
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* Multimedia card interface × 2 ch
 
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* Serial ATA interface × 1 ch
 
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* Media local bus (MLB) Interface × 1 ch (3 pin interface)
 
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* Controller Area Network (CAN-FD support) Interface × 2ch
 
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* Ethernet AVB 1.0-compatible MAC built in Interface: RGMII / Ethernet AVB (802.1BA)
 
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* SYS-DMAC x 48 ch, Realtime-DMAC x 16 ch,
 
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* Audio-DMAC x 32 ch, Audio(peripheral)-DMAC x 29 ch
 
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* 32bit timer x 26 ch
 
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* PWM timer × 7 ch
 
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* I2C bus interface × 7 ch
 
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* Serial communication interface (SCIF) × 11 ch
 
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* Quad serial peripheral interface (QSPI) x 2 ch (for boot, HyperFlash support)
 
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* Clock-synchronized serial interface (MSIOF) × 4 ch (SPI/IIS)
 
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* Ethernet controller (IEEE802.3u, RMII, without PHY)
 
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* Digital radio interface (DRIF) × 4 ch
 
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== Graphics ==
 
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{{integrated graphics
 
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| gpu                = PowerVR GX6650
 
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| designer            = Imagination Technologies
 
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}}
 
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== Features ==
 
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{{arm features
 
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|thumb=No
 
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|thumb2=No
 
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|thumbee=No
 
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|vfpv1=No
 
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|vfpv2=No
 
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|vfpv3=No
 
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|vfpv3-d16=No
 
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|vfpv3-f16=No
 
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|vfpv4=Yes
 
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|vfpv4-d16=No
 
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|vfpv5=No
 
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|neon=Yes
 
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|trustzone=Yes
 
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|jazelle=No
 
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|wmmx=No
 
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|wmmx2=No
 
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}}
 
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== Block Diagram ==
 
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:: [[File:r-car h3 block.png|750px]]
 
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== Die Shot ==
 
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* [[16 nm process]], CMOS FinFET
 
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* 12.94 mm × 8.61 mm
 
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* 111.36 mm² die size
 
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:: [[File:r-car h3 die shot.png|650px]]
 
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== References ==
 
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* Takahashi, Chikafumi, et al. "4.5 A 16nm FinFET heterogeneous nona-core SoC complying with ISO26262 ASIL-B: Achieving 10− 7 random hardware failures per hour reliability." Solid-State Circuits Conference (ISSCC), 2016 IEEE International. IEEE, 2016.
 

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Facts about "R-Car H3 (SiP) - Renesas"
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R-Car H3 (SiP) - Renesas#package +
core count9 +
core nameCortex-A53 +, Cortex-A57 + and Cortex-R7 +
core voltage0.8 V (8 dV, 80 cV, 800 mV) +
designerRenesas + and ARM Holdings +
die area111.36 mm² (0.173 in², 1.114 cm², 111,360,000 µm²) +
die length12.94 mm (1.294 cm, 0.509 in, 12,940 µm) +
die width8.61 mm (0.861 cm, 0.339 in, 8,610 µm) +
familyR-Car +
first announcedDecember 2, 2015 +
first launchedMarch 2018 +
full page namerenesas/r-car/h3 (sip) +
has ecc memory supportfalse +
instance ofmicroprocessor +
integrated gpuPowerVR GX6650 +
integrated gpu designerImagination Technologies +
io voltage3.3 V (33 dV, 330 cV, 3,300 mV) +
isaARMv8 +
isa familyARM +
l1$ size640 KiB (655,360 B, 0.625 MiB) +
l1d$ size288 KiB (294,912 B, 0.281 MiB) +
l1i$ size352 KiB (360,448 B, 0.344 MiB) +
l2$ size2.5 MiB (2,560 KiB, 2,621,440 B, 0.00244 GiB) +
ldateMarch 2018 +
main imageFile:r-car h3 (sip).png +
manufacturerTSMC +
market segmentEmbedded +
max cpu count1 +
max memory bandwidth47.68 GiB/s (48,824.32 MiB/s, 51.196 GB/s, 51,196.01 MB/s, 0.0466 TiB/s, 0.0512 TB/s) +
max memory channels4 +
microarchitectureCortex-A53 +, Cortex-A57 + and Cortex-R7 +
model numberH3 (SiP) +
nameR-Car H3 (SiP) +
packageFCBGA-1255 +
part numberR8J77950 +
process16 nm (0.016 μm, 1.6e-5 mm) +
series3rd Gen +
smp max ways1 +
supported memory typeLPDDR4-3200 +
technologyCMOS +
thread count9 +
word size64 bit (8 octets, 16 nibbles) +